參數(shù)資料
型號： 16F871
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 6 FT
中文描述： 28/40-Pin 8位CMOS閃存微控制器
文件頁數(shù)： 15/156頁
文件大小： 2816K
代理商： 16F871
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 15
PIC16F870/871
Bank 2
100h
(4)
101h
102h
(4)
103h
(4)
104h
(4)
105h
106h
107h
108h
109h
10Ah
(1,4)
10Bh
(4)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(4)
181h
182h
(4)
183h
(4)
184h
(4)
185h
186h
187h
188h
189h
18Ah
(1,4)
18Bh
(4)
18Ch
18Dh
18Eh
18Fh
Legend:
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
—
PORTB
—
—
—
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
xxxx xxxx
—
—
—
uuuu uuuu
—
—
—
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
EEDATA
EEADR
EEDATH
EEADRH
EEPROM data register
EEPROM address register
—
—
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
—
—
EEPROM data register high byte
—
EEPROM address register high byte
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
—
TRISB
—
—
—
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
—
—
1111 1111
—
—
—
1111 1111
—
—
—
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
EECON1
EECON2
—
—
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as ’0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3:
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4:
These registers can be addressed from any bank.
5:
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
EEPGD
EEPROM control register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
—
—
—
WRERR
WREN
WR
RD
x--- x000
x--- u000
---- ----
---- ----
0000 0000
0000 0000
0000 0000
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
(2)
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