參數(shù)資料
型號： 16F871
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 6 FT
中文描述： 28/40-Pin 8位CMOS閃存微控制器
文件頁數(shù)： 72/156頁
文件大?。?/td> 2816K
代理商： 16F871
PIC16F870/871
DS30569A-page 72
Preliminary
1999 Microchip Technology Inc.
FIGURE 9-7:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 9-8:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 9-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
x
= unknown,
-
= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
PSPIF
(1)
SPEN
USART Receive Register
PSPIE
(1)
CSRC
Baud Rate Generator Register
ADIF
RX9
RCIF
SREN
TXIF
CREN
—
CCP1IF
FERR
TMR2IF
OERR
TMR1IF
0000 -000
RX9D
0000 000x
0000 -000
ADDEN
0000 000x
0000 0000
0000 0000
ADIE
TX9
RCIE
TXEN
TXIE
SYNC
—
—
CCP1IE
BRGH
TMR2IE TMR1IE
0000 -000
TRMT
TX9D
0000 -000
0000 -010
0000 -010
0000 0000
0000 0000
Start
bit
bit1
bit0
bit8
bit0
Stop
bit
Start
bit
bit8
Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Bit8 = 0, Data Byte
Bit8 = 1, Address Byte
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN = 1.
Start
bit
bit1
bit0
bit8
bit0
Stop
bit
Start
bit
bit8
Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Bit8 = 1, Address Byte
Bit8 = 0, Data Byte
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(receive buffer) because ADDEN was not updated and still = 0.
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