參數(shù)資料
型號: 16F871
廠商: Microchip Technology Inc.
英文描述: CAT 5E CROSSOVER PATCH CORD CABLE GREEN 6 FT
中文描述: 28/40-Pin 8位CMOS閃存微控制器
文件頁數(shù): 134/156頁
文件大?。?/td> 2816K
代理商: 16F871
PIC16F870/871
DS30569A-page 134
Preliminary
1999 Microchip Technology Inc.
FIGURE 14-13: A/D CONVERSION TIMING
TABLE 14-10: A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
130
T
AD
A/D clock period
Standard(
F
)
1.6
3.0
2.0
3.0
4.0
6.0
6.0
9.0
12
μ
s
μ
s
μ
s
μ
s
T
AD
T
OSC
based, V
REF
3.0V
T
OSC
based, V
REF
2.0V
A/D RC Mode
A/D RC Mode
Extended(
LF
)
Standard(
F
)
Extended(
LF
)
131
T
CNV
Conversion time (not including S/H time)
(Note 1)
T
ACQ
Acquisition time
132
Note 2
10*
40
μ
s
μ
s
The minimum time is the ampli-
fier settling time. This may be
used if the "new" input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on C
HOLD
).
If the A/D clock source is
selected as RC, a time of T
CY
is
added before the A/D clock
starts. This allows the
SLEEP
instruction to be executed.
134
T
GO
Q4 to A/D clock start
T
OSC
/2 §
*
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
This specification ensured by design.
ADRES register may be read on the following T
CY
cycle.
See Section 10.1 for min conditions.
§
Note 1:
2:
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC
/2)
(1)
9
8
7
2
1
0
Note 1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
1 T
CY
. . .
. . .
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