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| 型號(hào)： | 16F871 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 6 FT |
| 中文描述： | 28/40-Pin 8位CMOS閃存微控制器 |
| 文件頁(yè)數(shù)： | 101/156頁(yè) |
| 文件大?。?/td> | 2816K |
| 代理商： | 16F871 |
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1999 Microchip Technology Inc.
Preliminary
DS30569A-page 101
PIC16F870/871
11.12
Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a
SLEEP
instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
.
FIGURE 11-10: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 11-11: SUMMARY OF WATCHDOG TIMER REGISTERS
Note:
The
CLRWDT
and
SLEEP
instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
Note:
When a
CLRWDT
instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h,181h
Legend:
Note 1:
See Register 11-1 for operation of these bits.
Config. bits
OPTION_REG
Shaded cells are not used by the Watchdog Timer.
(1)
BODEN
(1)
INTEDG
CP1
T0CS
CP0
T0SE
PWRTE
(1)
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
RBPU
From TMR0 Clock Source
(Figure 5-1)
To TMR0 (Figure 5-1)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
8
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