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參數(shù)資料
| 型號： | 16F871 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | CAT 5E CROSSOVER PATCH CORD CABLE GREEN 6 FT |
| 中文描述： | 28/40-Pin 8位CMOS閃存微控制器 |
| 文件頁數(shù)： | 24/156頁 |
| 文件大小： | 2816K |
| 代理商： | 16F871 |
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PIC16F870/871
DS30569A-page 24
Preliminary
1999 Microchip Technology Inc.
2.3
PCL and PCLATH
The Program Counter (PC) is 13-bits wide. The low
byte comes from the PCL Register, which is a readable
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 2-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
→
PCH). The lower example in the fig-
ure shows how the PC is loaded during a
CALL
or
GOTO
instruction (PCLATH<4:3>
→
PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1
COMPUTED GOTO
A computed
GOTO
is accomplished by adding an offset
to the program counter (
ADDWF PCL
). When doing a
table read using a computed
GOTO
method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note,
“Implementing a Table Read"
(AN556).
2.3.2
STACK
The PIC16FXXX family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a
CALL
instruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a
RETURN,RETLW
or a
RETFIE
instruction execu-
tion. PCLATH is not affected by a
PUSH
or
POP
opera-
tion.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4
Program Memory Paging
The PIC16FXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL
and
GOTO
instructions provide 11 bits of the
address, which allows branches within any 2K program
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16F872 has only 2K words of program memory or
one page, additional code is not required to ensure that
the correct page is selected before a
CALL
or
GOTO
instruction is executed. The PCLATH<4:3> bits should
always be maintained as zeros. If a return from a
CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.
2.5
Indirect Addressing, INDF and FSR
Registers
The INDF Register is not a physical register. Address-
ing the INDF Register will cause indirect addressing.
Indirect addressing is possible by using the INDF Reg-
ister. Any instruction using the INDF Register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR Register and the IRP bit
(STATUS<7>), as shown in Figure 2-4.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done
;no clear next
NEXT
CONTINUE
:
;yes continue
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
8
7
2
PCLATH
PCH
PCL
Note 1:
There are no status bits to indicate stack
overflow or stack underflow conditions.
2:
There are no instructions/mnemonics
called
PUSH
or
POP
. These are actions that
occur from the execution of the
CALL,
RETURN, RETLW
and
RETFIE
instruc-
tions or the vectoring to an interrupt
address.
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