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參數(shù)資料
| 型號： | 16F630 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 14-Pin FLASH-Based 8-Bit CMOS Microcontrollers |
| 中文描述： | 14引腳基于閃存的8位CMOS微控制器 |
| 文件頁數(shù)： | 22/132頁 |
| 文件大?。?/td> | 2651K |
| 代理商： | 16F630 |
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PIC16F630/676
DS40039C-page 20
2003 Microchip Technology Inc.
REGISTER 3-2:
TRISA — PORTA TRISTATE REGISTER (ADDRESS: 85h)
REGISTER 3-3:
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
3.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR'd together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTA. This will end the
mismatch condition.
b)
Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
U-0
U-0
R/W-x
R/W-x
R-1
R/W-x
R/W-x
R/W-x
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
bit 7-6:
Unimplemented
: Read as ’0’
bit 5-0:
TRISA<5:0>
: PORTA Tri-State Control bit
1
= PORTA pin configured as an input (tri-stated)
0
= PORTA pin configured as an output
Note:
TRISA<3> always reads 1.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
—
—
WPUA5
WPUA4
—
WPUA2
WPUA1
WPUA0
bit 7
bit 0
bit 7-6
Unimplemented:
Read as ‘0’
bit 5-4
WPUA<5:4>:
Weak Pull-up Register bit
1
= Pull-up enabled
0
= Pull-up disabled
bit 3
Unimplemented:
Read as ‘0’
bit 2-0
WPUA<2:0>:
Weak Pull-up Register bit
1
= Pull-up enabled
0
= Pull-up disabled
Note 1:
Global RAPU must be enabled for individual pull-ups to be enabled.
2:
The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
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