
2003 Microchip Technology Inc.
DS40039C-page 17
PIC16F630/676
2.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0>
→
PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a
CALL
or
GOTO
instruction (PCLATH<4:3>
→
PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1
COMPUTED
GOTO
A computed
GOTO
is accomplished by adding an offset
to the program counter (
ADDWF PCL
). When perform-
ing a table read using a computed
GOTO
method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note
“Implementing a Table Read"
(AN556).
2.3.2
STACK
The PIC16F630/676 family has an 8-level x 13-bit wide
hardware stack (see Figure 2-1). The stack space is
not part of either program or data space and the stack
pointer is not readable or writable. The PC is PUSHed
onto the stack when a
CALL
instruction is executed or
an interrupt causes a branch. The stack is POPed in
the event of a
RETURN,
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
RETLW
or a
RETFIE
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
8
7
2
PCLATH
PCH
PCL
Note 1:
There are no STATUS bits to indicate
stack
overflow
conditions.
or
stack
underflow
2:
There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW
and
RETFIE
instructions or the vectoring to an
interrupt address.