
PIC16F630/676
DS40039C-page 10
2003 Microchip Technology Inc.
TABLE 2-2:
PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOD
Page
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
1111 1111
18,61
12,30
81h
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0001 1xxx
17
11
83h
STATUS
IRP
(2)
RP1
(2)
RP0
TO
PD
Z
DC
C
84h
FSR
Indirect data memory address pointer
xxxx xxxx
--11 1111
—
--11 1111
—
—
---0 0000
0000 0000
00-- 0--0
—
---- --qq
18
19
—
—
—
—
17
13
14
—
16
85h
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
86h
—
Unimplemented
87h
TRISC
—
—
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
88h
—
Unimplemented
89h
—
Unimplemented
8Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of program counter
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
8Ch
PIE1
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE
8Dh
—
Unimplemented
8Eh
PCON
—
—
—
—
—
—
POR
BOD
8Fh
—
—
90h
OSCCAL
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
16
91h
ANSEL
(3)
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
—
—
—
--11 -111
46
—
—
—
20
92h
—
Unimplemented
93h
—
Unimplemented
94h
—
Unimplemented
95h
WPUA
—
—
WPUA5
WPUA4
—
WPUA2
WPUA1
WPUA0
96h
IOCA
—
—
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
—
—
0-0- 0000
0000 0000
0000 0000
---- x000
---- ----
xxxx xxxx
-000 ----
21
—
—
42
49
49
50
49
44
97h
—
Unimplemented
98h
—
Unimplemented
99h
VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0
9Ah
EEDAT
EEPROM data register
9Bh
EEADR
—
EEPROM address register
9Ch
EECON1
—
—
—
—
WRERR
WREN
WR
RD
9Dh
EECON2
ADRESL
(3)
ADCON1
(3)
EEPROM control register 2 (not a physical register)
9Eh
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
9Fh
—
ADCS2
ADCS1
ADCS0
—
—
—
—
45,61
Legend:
Note 1:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP & RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
2:
3: