參數(shù)資料
型號： (Z)PSD813F1
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 63/130頁
文件大?。?/td> 650K
代理商： (Z)PSD813F1
Prelimnary
PSD813F Famly
59
The
PSD813F
Functional
Blocks
(cont.)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, C, and D. The address input can be latched in the Input Micro
Cell
by the address strobe (ALE/AS). Any input that is included in the DPLD equations for the
PLD’s Flash, EEPROM, or SRAM is considered to be an address input.
9.4.2.5 Data Port Mode
Port A can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A if the port is configured as a Data Port.
9.4.2.6 Peripheral I/OMode
Peripheral I/O Mode can be used to interface with external peripherals. In this mode, all of
Port A serves as a tri-stateable, bi-directional data buffer for the microcontroller. Peripheral
I/O Mode is enabled by setting Bit 7 of the VM Register to a ‘1’. Figure 26 shows how Port A
acts as a bi-directional buffer for the microcontroller data bus if Peripheral I/O Mode is
enabled. An equation for PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is
tri-stated when PSEL 0 or 1 is not active.
9.4.2.7 JTAGISP
Port C is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port C because ISP is not performed
during normal system operation. For more information on the JTAG Port, refer to
section 9.6.
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 22 for the address output pin assignments on
Ports A and B for various MCUs.
For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in Address
Out Mode.
Note:
do not drive address lines with Address Out Mode to an external memory device if it
is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
80C251
(Page Mode)
N/A*
N/A
Address (7:4)
N/A
Address (11:8)
Address (11:8)
N/A
Address (15:12)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed Bus
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
N/A
N/A
Address [3:0]
Address [7:4]
Table 22. I/OPort Latched Address Output Assignments
N/A = Not Applicable.
相關(guān)PDF資料
PDF描述
(Z)PSD813F3 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，16K位SRAM)
(Z)PSD813F2(中文) Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
(Z)PSD813F3R(中文) Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM)
(Z)PSD813F2 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
(Z)PSD813F3R Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F1-12JI 制造商:WSI 功能描述:
ZPSD813F1-15J 制造商:WSI 功能描述:
ZPSD813F1-15U 制造商:WSI 功能描述:
ZPSD813F1-15UI 制造商:WSI 功能描述:
ZPSD813F1-90U 制造商:WSI 功能描述:
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