參數(shù)資料
型號： (Z)PSD813F1
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 17/130頁
文件大小： 650K
代理商： (Z)PSD813F1
Prelimnary
PSD813F Famly
13
Table 5.
PSD813F
Pin
Descriptions
(cont.)
Pin Name
Pin*
Type
Description
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro
Cell (McellBC7) output.
3. Input to the PLDs.
4. DBE — active-low Data Byte Enable input from 68HC912
type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
port.
3. Input to the PLDs.
4. CPLD output (external chip select).
PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CLKIN — clock input to the CPLD Micro
Cells, the
automatic power-down unit’s power-down counter, and
the CPLD AND array.
PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CSI — chip select input. When low, the MCU can access
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
Power pins
Ground pins
PD0
10
I/O
PD1
9
I/O
PD2
8
I/O
V
CC
GND
15, 38
1,16,26
Port A
Port A (7:4)
Address [7:4]
N/A
Port B
Microcontroller
8051XA (8-bit)
80C251 (page mode)
All other 8-bit
multiplexed
8-bit non-multiplexed
bus
Port A (3:0)
N/A
N/A
Port B (3:0)
Address [11:8]
Address [11:8]
Port B (7:4)
N/A
Address [15:12]
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
N/A
N/A
Address [3:0]
Address [7:4]
Table 6. I/OPort Latched Address Output Assignments*
N/A = Not Applicable
*
*
Refer to the I/O Port Section on how to enable the Latched Address Output function.
*
*
The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
**
These functions can be multiplexed with other functions.
相關(guān)PDF資料
PDF描述
(Z)PSD813F3 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲器，16K位SRAM)
(Z)PSD813F2(中文) Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
(Z)PSD813F3R(中文) Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM)
(Z)PSD813F2 Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位和256K位閃速存儲器，16K位SRAM)
(Z)PSD813F3R Multi-Chip-Module to Monolithic Flash PSD(閃速，在系統(tǒng)可編程微控制器外圍器件，0M位閃速存儲器，無SRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD813F1-12JI 制造商:WSI 功能描述:
ZPSD813F1-15J 制造商:WSI 功能描述:
ZPSD813F1-15U 制造商:WSI 功能描述:
ZPSD813F1-15UI 制造商:WSI 功能描述:
ZPSD813F1-90U 制造商:WSI 功能描述:
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