參數(shù)資料
型號: (Z)PSD813F1
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(shè)(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬位閃速存儲器,256K位的EEPROM,16K的位的SRAM)
文件頁數(shù): 104/130頁
文件大小: 650K
代理商: (Z)PSD813F1
PSD813F Family
Preliminary
100
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
28
30
Address Setup Time
(Note 1)
10
12
ns
Address Hold Time
(Note 1)
12
14
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
30
35
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
t
WHAX
t
WHPV
CS Valid to Leading Edge of WR
(Note 3)
34
40
ns
WR Data Setup Time
(Note 3)
45
50
ns
WR Data Hold Time
(Note 3)
8
10
ns
WR Pulse Width
(Note 3)
48
53
ns
Trailing Edge of WR to Address Invalid
(Note 3)
0
0
ns
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
45
50
ns
t
WLMV
WR Valid to Port Output Valid Using
Micro
Cell Register Preset/Clear
Byte Programming Operation
(Notes 3 and 4)
90
100
ns
t
WHQV1
Also including
pre-programming time
14
14
μs
t
WHQV2
t
Q7VQV
Sector Erase Operation
Note 100% tested
2.2
2.2
sec
Q7 Valid to Output Valid (Data Polling)
70
75
ns
t
VCS
V
CC
Setup Time
V
CC
High to First Flash WR Low
Data Valid to Port Output Valid
Using Micro
Cell Register Preset/Clear
Address Input Valid to Address
Output Delay
45
50
μs
t
DVMV
(Notes 3 and 5)
90
100
ns
t
AVPV
(Note 2)
48
55
ns
Write, Erase and Program Timing
(2.7 V to 3.6 V Versions)
NOTES:
1. Any input used to select an internal PSD813F function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
Microcontroller Interface – ZPSD813FV AC/DC Parameters
(2.7 V to 3.6 V Versions)
相關(guān)PDF資料
PDF描述
(Z)PSD813F3 Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲器,16K位SRAM)
(Z)PSD813F2(中文) Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲器,16K位SRAM)
(Z)PSD813F3R(中文) Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲器,無SRAM)
(Z)PSD813F2 Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲器,16K位SRAM)
(Z)PSD813F3R Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲器,無SRAM)
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