參數(shù)資料
型號(hào): (Z)PSD813F1
英文描述: Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲(chǔ)器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程Mirocomputer外設(shè)(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬(wàn)位閃速存儲(chǔ)器,256K位的EEPROM,16K的位的SRAM)
文件頁(yè)數(shù): 12/130頁(yè)
文件大小: 650K
代理商: (Z)PSD813F1
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PSD813F Famly
Prelimnary
8
5.7 In-SystemProgrammng
Using the JTAG signals on Port C, the entire PSD813F device can be programmed or
erased without the use of the microcontroller. The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out
of the optional EEPROM, Flash Boot memory, or SRAM. The optional EEPROM or Flash
Boot memory can be programmed the same way by executing out of the main Flash
memory. The PLD logic or other PSD813F configuration can be programmed through the
JTAG port or a device programmer. Table 4 indicates which programming methods can
program different functional blocks of the PSD813F.
PSD813F
Architectural
Overview
(cont.)
JTAG
Device
Programmer
In-SystemParallel
Programmng
Functional Block
Programmng
Main Flash memory
Yes
Yes
Yes
Optional EEPROM/Flash Boot
memory
Yes
Yes
Yes
PLD Array (DPLD
and CPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Optional OTP Row
No
Yes
Yes
Table 4. Methods of Programmng Dfferent Functional Blocks of the PSD813F
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD813F gives the user control of the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The ZPSD813F also has some bits that are configured at run-time by the MCU to reduce
power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off and
the CPLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the CPLD to reduce power consumption. See section 9.5.
相關(guān)PDF資料
PDF描述
(Z)PSD813F3 Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲(chǔ)器,16K位SRAM)
(Z)PSD813F2(中文) Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲(chǔ)器,16K位SRAM)
(Z)PSD813F3R(中文) Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲(chǔ)器,無(wú)SRAM)
(Z)PSD813F2 Flash In System Programmable Mirocomputer Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位和256K位閃速存儲(chǔ)器,16K位SRAM)
(Z)PSD813F3R Multi-Chip-Module to Monolithic Flash PSD(閃速,在系統(tǒng)可編程微控制器外圍器件,0M位閃速存儲(chǔ)器,無(wú)SRAM)
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