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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	421/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

CHAPTER 6 USB CONTROLLER

Preliminary User’s Manual S14767EJ1V0UM00

Numbers (1) to (15) do not indicate the order in which USB Controller must perform processing. Instead, these

numbers correspond to those in the following explanation.

USB Controller starts send processing upon receiving a send command from the V

4120A RISC Processor.

At the instant that the command is written, USB Controller checks whether the Busy bit (Bit 31) of the USB

Command Register is set.

Set Busy Bit of USB Command Register to “1”.

If the Busy bit (Bit 31) of the USB Command Register is set, the command written in (1) is ignored.

USB Controller checks whether the EndPoint specified with the send command is currently in the Busy

status (two items of data are scheduled to be sent).

If the EndPoint specified with the send command is found to be in the Busy status, the command written in

(1) is ignored.

The command written into the USB Command Register and USB Command Address Register in (1) is

copied to an internal register and the Busy bit of the USB Command Register is returned to 0.

USB Controller reads the buffer descriptor that contains the value that is written into the USB Command

Address Register at the same time as the send command.

USB Controller compares the size of the area remaining in the send FIFO with the buffer size of the buffer

descriptor read in the previous step.

(10) If step (8) reveals that the area remaining in the send FIFO is smaller, USB Controller DMA- transfers the

data from the buffer until the send FIFO is full.

(11) Once the send FIFO is full, USB Controller transfers the data to the USB.

(12) If step (8) reveals that the area remaining in the send FIFO is larger, USB Controller DMA-transfers all the

data in the buffer to the send FIFO.

(13) USB Controller checks whether the DMA-transferred data is the last data of the data segments to be sent

(14) If the DMA-transferred data is not the last to be sent, it indicates that the buffer is empty. Therefore, USB

Controller reads the next buffer descriptor.

(15) If the DMA-transferred data is the last to be sent, USB Controller writes a Tx indication in the mailbox.

(16) USB Controller updates the mailbox write pointer (USB Tx MailBox Write Address Register). It also sets

the send completion bit of the USB General Status Register1 and, provided it is not masked, issues an

interrupt to the V

4120A RISC Processor.

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