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Preliminary User’s Manual S14767EJ1V0UM00
6.6.5 V
R
4120A RISC processor receive processing..................................................................................430
6.6.6 USB controller receive processing ...................................................................................................431
6.6.7 Detection of errors on USB ..............................................................................................................434
6.6.8 Rx data corruption on isochronous EndPoint ...................................................................................436
6.6.9 Rx FIFO overrun...............................................................................................................................437
6.6.10 Rx indication...................................................................................................................................438
Power Management.................................................................................................................440
6.7.1 Suspend...........................................................................................................................................440
6.7.2 Resume............................................................................................................................................441
6.7.3 Remote wake up ..............................................................................................................................442
Loopback Mode .......................................................................................................................443
Example of Connection...........................................................................................................444
6.7
6.8
6.9
CHAPTER 7 UART................................................................................................................................445
7.1
Overview...................................................................................................................................445
7.2
UART Block Diagram...............................................................................................................445
7.3
UART Registers .......................................................................................................................446
7.3.1 UART Receiver data Buffer Register (UARTRBR) (80H, DLAB = 0, R)...........................................446
7.3.2 UART Interrupt Enable Register (UARTIER) (84H, DLAB = 1, R/W) ...............................................446
7.3.3 UART Divisor Latch LSB Register (UARTDLL) (80H, DLAB = 1, R/W)............................................447
7.3.4 UART Divisor Latch MSB Register (UARTDLM) (84H, DLAB = 1, R/W)..........................................447
7.3.5 UART Interrupt ID Register (UARTIIR) (88H, R)..............................................................................449
7.3.6 UART FIFO Control Register (UARTFCR) (88H, W)........................................................................450
7.3.7 UART Line Control Register (UARTLCR) (8CH, R/W).....................................................................451
7.3.8 UART Modem Control Register (UARTMCR) (90H, R/W)................................................................452
7.3.9 UART Line Status Register (UARTLSR) (94H, R/W) .......................................................................453
7.3.10 UART Modem Status Register (UARTMSR) (98H, R/W) ...............................................................454
7.3.11 UART Scratch Register (UARTSCR) (9CH, R/W)..........................................................................455
CHAPTER 8 TIMER...............................................................................................................................457
8.1
Overview...................................................................................................................................457
8.2
Block Diagram..........................................................................................................................457
8.3
Timer Registers........................................................................................................................458
8.3.1 Timer Mode Register (TMMR) (B0H, R/W) ......................................................................................458
8.3.2 Timer CH0 Count Set Register (TM0CSR) (B4H, R/W) ...................................................................458
8.3.3 Timer CH1 Count Set Register (TM1CSR) (B8H, R/W) ...................................................................458
8.3.4 Timer CH0 Current Count Register (TM0CCR) (BCH, R) ................................................................458
8.3.5 Timer CH1 Current Count Register (TM1CCR) (C0H, R).................................................................459
CHAPTER 9 MICRO WIRE ..................................................................................................................461
9.1
Overview...................................................................................................................................461
9.2
Micro Wire Connection Diagram............................................................................................461
9.3
Operations................................................................................................................................462
9.3.1 Data read at the power up load........................................................................................................462
9.3.2 Accessing to EEPROM ....................................................................................................................462
9.4
Registers...................................................................................................................................463
9.4.1 ECCR (EEPROM Command Control Register) Address 1000_00D0h [Write Only].......................463
9.4.2 ERDR (EEPROM Read Data Register) Address 1000_00D4h [Read Only] ..................................463