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型號(hào)：	μPD98501
廠商：	NEC Corp.
英文描述：	Network Controller(網(wǎng)絡(luò)控制器)
中文描述：	網(wǎng)絡(luò)控制器（網(wǎng)絡(luò)控制器）
文件頁(yè)數(shù)：	129/671頁(yè)
文件大?。?/td>	2229K
代理商：	ΜPD98501

Preliminary User’s Manual S14767EJ1V0UM00

2.4.5.3 Slip conditions

2 of the RF stage and

1 of the EX stage, internal logic will determine whether it is possible to start the

current instruction in this cycle. If all of the source operands are available (either from the register file or via the

internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever

required, then the instruction “run”; otherwise, the instruction will “slip”. Slipped instructions are retired on subsequent

cycles until they issue. The backend of the pipeline (stages DC and WB) will advance normally during slips in an

attempt to resolve the conflict. NOPs will be inserted into the bubble in the pipeline. Instructions killed by branch

likely instructions, ERET or exceptions will not cause slips.

Figure 2-33. Load Data Interlock

Detect load interlock

Get the target data

Load Data Interlock is detected in the RF stage shown in as Figure 2-33 and also the pipeline slips in the stage.

Load Data Interlock occurs when data fetched by a load instruction and data moved from HI, LO or CP0 registers is

required by the next immediate instruction. The pipeline begins running again when the clock after the target of the

load is read from the data cache, HI, LO and CP0 registers. The data returned at the end of the DC stage is input into

the end of the RF stage, using the bypass multiplexers.

Figure 2-34. MD Busy Interlock

Detect MD busy interlock

Get target data

MD Busy Interlock is detected in the RF stage as shown in Figure 2-34 and also the pipeline slips in the stage. MD

Busy Interlock occurs when HI/LO register is required by MFHI/MFLO instruction before finishing Mult/Div execution.

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