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CHAPTER 4 ATM CELL PROCESSOR
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Preliminary User’s Manual S14767EJ1V0UM00
When the L flag of the current transmit buffer indicates that the buffer is the last one and the value in the field
indicating the number of bytes remaining in the VC table is less than 40 bytes, the cell is the last cell of the
packet.
<1> If the current cell is the last cell of the packet, and the remaining payload data is less than 40 bytes, zero
padding and the 8 byte trailer are added. If the remaining payload data is more than 40 bytes and there
are not enough space to add an 8-byte AAL-5 trailer, ATM Cell Processor just adds zero padding to make
48 byte payload and ATM Cell Processor sends a cell containing only a trailer and padding next.
<2> When the last segment of the AAL-5 PDU is read, the final CRC-32 value and the packet length are
inserted into the trailer of the AAL-5 PDU, and the contents of the first word in the VC table are inserted
into the CPCS-UU and CPI fields, thereby completing the AAL-5 trailer.
(g) ATM Cell Processor checks whether there is a subsequent packet ( checks Last Packet Info address and First
Packet Info address in Tx VC table). When a subsequent packet exists, (e) and (f) are repeated.
(h) For each packet, ATM Cell Processor stores transmitting indication as a status information in the mailbox and
generates an interrupt.
(i) V
R
4120A RISC Processor reads the mailbox and updates the read pointer of the mailbox.
(2) IPoA mode
(a) Setting transmitting data
Before transmitting a packet, V
R
4120A RISC Processor stores transmitting data in SDRAM and sets the packet
descriptor. In IPoA mode, the transmitting data should be a IP packet.
(b) Opening the send channel
If V
R
4120A RISC Processor needs a new channel for transmission, V
R
4120A RISC Processor issues
Open_Channel command. When this command is issued, ATM Cell Processor assigns the new block from the
VC Table pool in Work RAM and reports its start address to V
R
4120A RISC Processor using a command
indication. V
R
4120A RISC Processor sets the assigned block as a send VC address.
(c) Setting the send VC table
The 16-word block assigned from the VC Table pool in Work RAM is set as the send VC table for each VC.
(d) Opening the IP flow
If the IP flow has not registered yet, V
R
4120A RISC Processor issues Open_IP_Channel command. When this
command is issued, ATM Cell Processor assigns the 3 words block for flow table and reports its start address
to V
R
4120A RISC Processor using command indication. V
R
4120A RISC Processor sets the IP flow information
and VC number in the flow table.
(e) Issuing the IP_Flow_Ready command
When V
R
4120A RISC Processor issues the IP_Flow_Ready command, ATM Cell Processor sets the H/W IP
lookup table using the data which V
R
4120A RISC Processor sets in the IP Flow table.
(f) Issuing the Tx_Ready command -> making preparations for sending of the first cell
When V
R
4120A RISC Processor issues the Tx_Ready command, ATM Cell Processor sets the Packet Info
structure in the Work RAM and fetches the packet descriptor using Scatter/Gather DMA and store it in the area.
ATM Cell Processor also fetches the first segment to the Work RAM using Scatter/Gather DMA. Then, ATM
Cell Processor searches if the IP Flow exist in IP Lookup Table using the IP header information in the first
segment. If IP Flow is found, ATM Cell Processor gets the corresponding VC number.
(g) Sending a single cell
<1> Generating a header
A header is generated from Word1 in the VC table and written into SAR FIFO. "00H" is inserted into the
GFC field of the header.
<2> Generate LLC or PPP header if needed