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CHAPTER 6 USB CONTROLLER
388
Preliminary User’s Manual S14767EJ1V0UM00
6.2.2.12
USB EP5 Control Register (U_EP5CR): 34H
31
MAXP5
15
0
7
Reserved
Reserved
30
6
EP5EN
16
NAK5
R
SS5
17
18
19
FM
Register for setting the operation of EndPoint5.
If the value in the MAXP field is rewritten during a send or receive operation, the operation of USB Controller may
become unpredictable. Therefore the MAXP can be written to once only, when initial setting is being performed.
Bit
Field
Description
R/W
31
EP5EN
(EndPoint Enable)
If the V
R
4120A RISC processor sets this bit to 1, EndPoint5 is enabled for
transmitting and receiving data from and to USB.
R/W
30-20
Reserved
Reserved for future use
R
19
FM
(Feedback Mode)
If the V
R
4120A RISC Processor sets this bit to 1, EndPoint5 performs in
feedback mode.
(For further information about Feedback mode, please refer to USB
Specification 1.1)
R/W
18
SS5
(Send Stall)
If the V
R
4120A RISC Processor sets this bit to 1, STALL handshake is
performed at EndPoint5.
R/W
17
Reserved
Reserved for future use
R
16
NAK5
If the V
R
4120A RISC processor sets this bit to 1, NAK Handshake is
performed at EndPoint5.
R/W
15-7
Reserved
Reserved for future use
R
6-0
MAXP5
(MAX Packet size)
Register that stores the Max Packet Size for EndPoint5. Prior to the start of
a USB transaction, the V
R
4120A RISC Processor must write an appropriate
value into this register.
When this field contains 0, no transaction is performed at EndPoint5.
R/W