XRT86VL3X
VI
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
Figure 104.: T1 Extended Superframe Format .............................................................................................................. 115
Figure 105.: T1DM Frame Format ................................................................................................................................. 117
Figure 106.: Framer System Transmit Timing Diagram (Base Rate/Non-Mux) ............................................................. 121
Figure 107.: Framer System Receive Timing Diagram (RxSERCLK as an Output) ...................................................... 122
Figure 108.: Framer System Receive Timing Diagram (RxSERCLK as an Input) ......................................................... 123
Figure 109.: Framer System Transmit Timing Diagram (HMVIP and H100 Mode) ....................................................... 124
Figure 110.: Framer System Receive Timing Diagram (HMVIP/H100 Mode) ............................................................... 125
Figure 111.: Framer System Transmit Overhead Timing Diagram ................................................................................ 126
Figure 112.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Output) ..................................... 127
Figure 113.: Framer System Receive Overhead Timing Diagram (RxSERCLK as an Input) ........................................ 127
Figure 114.: ITU G.703 Pulse Template ........................................................................................................................ 131
Figure 115.: DSX-1 Pulse Template (normalized amplitude) ........................................................................................ 132
Figure 116.: Intel μP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Not Tied ’HIGH’
134
Figure 117.: Intel μP Interface Timing During Programmed I/O Read and Write Operations When ALE Is Tied ’HIGH’ 135
Figure 118.: Motorola Asychronous Mode Interface Signals During Programmed I/O Read and Write Operations ..... 136
Figure 119.: Power PC 403 Interface Signals During Programmed I/O Read and Write Operations ........................... 137