XRT86VL3X
VII
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
LIST OF TABLES
Table 1:: Bit Ordering and Usage ....................................................................................................................................26
Table 2:: Framing Format for PMON Status Inserted within LAPD by Initiating APR ......................................................27
Table 3:: Random Bit Sequence Polynomials ..................................................................................................................44
Table 4:: Short Haul Line Build Out .................................................................................................................................47
Table 5:: Selecting the Internal Impedance .....................................................................................................................49
Table 6:: Mapping a T1 Frame into an E1 Frane .............................................................................................................70
Table 7:: Bit Format of Timeslot 0 octet within a FAS E1 Frame ...................................................................................108
Table 8:: Bit Format of Timeslot 0 octet within a Non-FAS E1 Frame ...........................................................................109
Table 9:: Bit Format of all Timeslot 0 octets within a CRC Multi-frame ..........................................................................110
Table 10:: Superframe Format .......................................................................................................................................114
Table 11:: Extended Superframe Format .......................................................................................................................116
Table 12:: Non-Signaling Framing Format .....................................................................................................................117
Table 13:: SLC96 Fs Bit Contents ...............................................................................................................................118
Table 14:: XRT86VL32 Power Consumption ................................................................................................................119
Table 15:: XRT86VL34 Power Consumption ................................................................................................................120
Table 16:: XRT86VL38 Power Consumption ................................................................................................................120
Table 17:: E1 Receiver Electrical Characteristics ..........................................................................................................128
Table 18:: T1 Receiver Electrical Characteristics ..........................................................................................................129
Table 19:: E1 Transmit Return Loss Requirement .........................................................................................................129
Table 20:: E1 Transmitter Electrical Characteristics ......................................................................................................130
Table 21:: T1 Transmitter Electrical Characteristics ......................................................................................................130
Table 22:: Transmit Pulse Mask Specification ...............................................................................................................131
Table 23:: DSX1 Interface Isolated pulse mask and corner points ................................................................................132
Table 24:: AC Electrical Characteristics .........................................................................................................................133
Table 25:: Intel Microprocessor Interface Timing Specifications ....................................................................................134
Table 26:: Intel Microprocessor Interface Timing Specifications ....................................................................................135
Table 27:: Motorola Asychronous Mode Microprocessor Interface Timing Specifications .............................................136
Table 28:: Power PC 403 Microprocessor Interface Timing Specifications ...................................................................137