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參數(shù)資料
| 型號(hào)： | XRT86VL3X |
| 廠商： | Exar Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 4/149頁(yè) |
| 文件大?。?/td> | 1274K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
I
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
LIST OF PARAGRAPHS
1.0 GENERAL DESCRIPTION AND INTERFACE .........................................................................................4
1.1 PHYSICAL INTERFACE ......................................................................................................................................4
1.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ....................................................5
1.2.1 LINE CARD REDUNDANCY ........................................................................................................................................... 5
1.2.2 TYPICAL REDUNDANCY SCHEMES ............................................................................................................................ 5
1.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS ........................................................................................................ 5
1.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ...................................................................................... 5
1.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ......................................................................................... 6
1.3 POWER FAILURE PROTECTION .......................................................................................................................7
1.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ....................................................................................7
1.5 NON-INTRUSIVE MONITORING .........................................................................................................................7
1.6 T1/E1 SERIAL PCM INTERFACE .......................................................................................................................8
1.7 T1/E1 FRACTIONAL INTERFACE ......................................................................................................................9
1.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL .......................................................................................10
1.9 ROBBED BIT SIGNALING/CAS SIGNALING ...................................................................................................11
1.10 OVERHEAD INTERFACE ................................................................................................................................12
1.11 FRAMER BYPASS MODE ...............................................................................................................................14
1.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE ..........................................................................................15
1.13 HIGH-SPEED MULTIPLEXED INTERFACE ...................................................................................................16
2.0 LOOPBACK MODES OF OPERATION .................................................................................................17
2.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS ..............................................................................17
2.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................... 17
2.1.2 REMOTE LOOPBACK .................................................................................................................................................. 17
2.1.3 DIGITAL LOOPBACK ................................................................................................................................................... 18
2.1.4 DUAL LOOPBACK ....................................................................................................................................................... 18
2.1.5 FRAMER REMOTE LINE LOOPBACK ........................................................................................................................ 19
2.1.6 FRAMER LOCAL LOOPBACK ..................................................................................................................................... 19
2.2 PROGRAMMING SEQUENCE FOR SENDING LESS THAN 96-BYTE MESSAGES ......................................20
2.3 PROGRAMMING SEQUENCE FOR SENDING LARGE MESSAGES .............................................................20
2.4 PROGRAMMING SEQUENCE FOR RECEIVING LAPD MESSAGES .............................................................21
2.5 SS7 (SIGNALING SYSTEM NUMBER 7) FOR ESF IN DS1 ONLY ..................................................................21
2.6 DS1/E1 DATALINK TRANSMISSION USING THE HDLC CONTROLLERS ...................................................21
2.7 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR .......................................................................21
2.7.1 DESCRIPTION OF BOS ................................................................................................................................................ 21
2.7.2 PRIORITY CODEWORD MESSAGE ............................................................................................................................ 22
2.7.3 COMMAND AND RESPONSE INFORMATION ............................................................................................................ 22
2.8 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) PROCESSOR ..........................................................22
2.8.1 DISCUSSION OF MOS ................................................................................................................................................. 22
2.8.2 PERIODIC PERFORMANCE REPORT ........................................................................................................................ 23
2.8.3 TRANSMISSION-ERROR EVENT ................................................................................................................................ 23
2.8.4 PATH AND TEST SIGNAL IDENTIFICATION MESSAGE ........................................................................................... 24
2.8.5 FRAME STRUCTURE ................................................................................................................................................... 24
2.8.6 FLAG SEQUENCE ........................................................................................................................................................ 24
2.8.7 ADDRESS FIELD .......................................................................................................................................................... 24
2.8.8 ADDRESS FIELD EXTENSION BIT (EA) ..................................................................................................................... 24
2.8.9 COMMAND OR RESPONSE BIT (C/R) ........................................................................................................................ 24
2.8.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ........................................................................................................ 25
2.8.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ................................................................................................................. 25
2.8.12 CONTROL FIELD ........................................................................................................................................................ 25
2.8.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................... 25
2.8.14 TRANSPARENCY (ZERO STUFFING) ....................................................................................................................... 25
2.9 TRANSMIT SLC96 DATA LINK CONTROLLER ............................................................................................26
2.10 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................27
2.11 AUTOMATIC PERFORMANCE REPORT (APR) ............................................................................................27
2.11.1 BIT VALUE INTERPRETATION ................................................................................................................................. 27
3.0 OVERHEAD INTERFACE BLOCK ........................................................................................................29
3.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................................................29
3.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................ 29
3.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA
LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ................................................................................................. 29
3.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING
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