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| 型號(hào)： | XRT86VL3X |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 31/149頁(yè) |
| 文件大?。?/td> | 1274K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
24
REV. 1.2.0
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
terminal has lost framing, is only designed as a performance indicator; existing terminal out-of-frame criteria
will continue to serve as the basis for terminal alarms.
Frame-Synchronization-Bit Error Event: A frame-synchronization-bit-error event is the occurrence of a
received framing-bit-pattern not meeting the severely-errored-framing event criteria.
Line-Code Violation event: A line-code violation event is a bipolar violation of the incoming data. A line-code
violation event for an B8ZS-coded signal is the occurrence of a received excessive zeros (EXZ) or a bipolar
violation that is not part of a zero-substitution code.
Controlled Slip Event: A controlled-slip event is a replication, or deletion, of a T1 frame by the receiving
terminal. A controlled slip may occur when there is a difference between the timing of a synchronous
receiving terminal and the received signal.
2.8.4
Path and Test Signal Identification Message
The path identification message is used to identify the path between the source terminal and the sink terminal.
The test signal identification message is used by test signal generating equipment. Both identification
messages are made up of 82 bytes of data. Byte 1 to 4, 81 and 82 are the message header and bytes 5 to 80
contain six data elements. These messages use the SAPI/TEI value of 0x15 to differentiate themselves from
the performance report message.
2.8.5
Frame Structure
The message structure of message-oriented signal is shown in
Figure 29
. Two format types are shown in the
figure: format A for frames which are sending performance report message and format B for frames which
containing a path or test signal identification message. The following abbreviations are used:
SAPI: Service Access Point Identifier
C/R: Command or Response
EA: Extended Address
TEI: Terminal Endpoint Identifier
FCS: Frame Check Sequence
2.8.6
Flag Sequence
All frames shall start and end with the flag sequence consisting of one 0 bit followed by six contiguous 1 bits
and one 0 bit. The flag preceding the address field is defined as the opening flag. The flag following the Frame
Check Sequence (FCS) field is defined as the closing flag. The closing flag may also serve as the opening flag
of the next frame, in some applications. However, all receivers must be able to accommodate receipt of one or
more consecutive flags.
2.8.7
Address Field
The address field consists of two octets. A single octet address field is reserved for LAPB operation in order to
allow a single LAPB data link connection to be multiplexed along with LAPD data link connections.
2.8.8
Address Field Extension bit (EA)
The address field range is extended by reserving bit 1 of the address field octets to indicate the final octet of
the address field. The presence of a 1 in bit 1 of an address field octet signals that it is the final octet of the
address field. The double octet address field for LAPD operation shall have bit 1 of the first octet set to a 0 and
bit 1 of the second octet set to 1.
2.8.9
Command or Response bit (C/R)
The Command or Response bit identifies a frame as either a command or a response. The user side shall
send commands with the C/R bit set to 0, and responses with the C/R bit set to 1. The network side shall do the
opposite; That is, commands are sent with C/R bit set to 1, and responses are sent with C/R bit set to 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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