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參數(shù)資料
| 型號： | XRT86VL3X |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 28/149頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
21
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.0
7.
Re-initiate the TxSOT interrupt enable.
8.
Write 0xE0 into the transmit byte count register (buffer 1).
9.
Write the next 96-bytes into 0xn700 (buffer 1, automatically incremented).
10.
Enable the LAPD transmission by writing to register 0xn113.
11.
Wait for the TxSOT before writing the next 96-bytes.
12.
Continue until the entire message is sent.
2.4
Programming Sequence for Receiving LAPD Messages
The XRT86VL3x can extract data link information from incoming DS1 frames from either the datalink bits
themselves or the D/E time slots within the PCM input data. To extract a LAPD message, the following
programming sequence can be used as a reference.
1.
Enable RxEOT in the Data Link Interrupt Enable Register.
2.
Wait for the RxEOT interrupt to occur.
3.
Once RxEOT occurs, read the Receive Data Link Byte Count Register to determine which buffer the data is
extracted to and how many bytes are contained within the message.
4.
Read the exact amount of bytes from the proper buffer. If buffer 0, read 0xn600. If buffer 1, read 0xn700. These
two registers are automatically incremented.
2.5
SS7 (Signaling System Number 7) for ESF in DS1 Only
To support SS7 specifications while receiving LAPD messages, EXAR’s Framer will generate an interrupt (if
SS7 is enabled) once the HDLC controllers have received more than 276 bytes within two flag sequences
(0x7E) of a LAPD message. Each HDLC controller supports SS7. For example: To enable SS7 for all HDLC
controllers, registers 0xnB11 (LAPD1), 0xnB19 (LAPD2), 0xnB29 (LAPD3) must be set to 0x01.
2.6
DS1/E1 Datalink Transmission Using the HDLC Controllers
The transmit framer block can insert data link information to outbound DS1/E1 frames. The data link
information can be inserted from the following sources.
Transmit Overhead Input Interface (TxOH)
Transmit HDLC1 Controller
Transmit Serial Input Interface (TxSER)
N
OTE
:
HDLC1 is the dedicated controller for transmission of LAPD messages through the datalink bits. If the datalink bits
are not used for LAPD messages, then HDLC1 can be used through the D/E time slots as with HDLC2 and HDLC3.
The Transmit Data Link Source Select bits within the Transmit Data Link Select Register (TSDLSR) determine
the source for the data link bits in ESF, SLC96, or T1DM for DS1 and CRC multi frame for E1. Each Transmit
HDLC Controller contains four major functional modules.
Bit-Oriented Signaling Processor
LAPD Controller
SLC96 Data Link Controller
Automatic Performance Report (APR) Generation
2.7
Transmit BOS (Bit Oriented Signaling) Processor
The Transmit BOS Processor handles transmission of BOS messages through the data link channel. The
processor can be set for a specific amount of repetitions a certain BOS message will be transmitted, or it may
be placed in an infinite loop. The processor can also insert a BOS IDLE flag sequence and/or an ABORT
sequence to be transmitted on the data link channel.
2.7.1
Description of BOS
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