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參數(shù)資料
| 型號(hào)： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 94/153頁(yè) |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X |
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XRT86VL3X
87
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
Sixteen-code signaling is implemented by substituting the LSB of channel data in frames 6, 12, 18, and 24 with
the content of Signaling bit A, B, C, and D of TSCR register respectively.
In N or T1DM modes, no robbed-bit signaling is allowed and the transmit data stream remains intact.
The table below shows the four most significant bits of the Transmit Signaling Control Register.
8.3.3
Insert Signaling Bits from TxSig_n Pin
The XRT86VL3x framer can be configured to insert signaling bits provided by external equipment through the
TxSig_n pins. This pin is a multiplexed I/O pin with two functions:
TxCHN[0]_n - Transmit Timeslot Number Bit [0] Output pin
TxSig_n - Transmit Signaling Input pin
When the Transmit Fractional DS1 bit of the Transmit Interface Control Register (TICR) is set to 0, this pin is
configured as TxTSb[0]_n pin, it outputs bit 0 of the timeslot number of the DS1 PCM data that is transmitting.
When the Transmit Fractional DS1 bit of the Transmit Interface Control Register (TICR) is set to 1, this pin is
configured as TxSig_n pin, it acts as an input source for the signaling bits to be transmitted in the outbound
DS1 frames.
Figure 93
below is a timing diagram of the TxSig_n input pin. Please note that the Signaling Bit A of a certain
timeslot coincides with Bit 4 of the PCM data; Signaling Bit B coincides with Bit 5 of the PCM data; Signaling Bit
C coincides with Bit 6 of the PCM data and Signaling Bit D coincides with Bit 7 (LSB) of the PCM data.
TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (ADDRESS = 0XN340H - 0XN357H)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
7
Signaling Bit A
R/W
This bit is used to store Signaling Bit A that is sent as the least significant
bit of timeslot of frame number 6.
6
Signaling Bit B
R/W
This bit is used to store Signaling Bit B that is sent as the least significant
bit of timeslot of frame number 12.
5
Signaling Bit C
R/W
This bit is used to store Signaling Bit C that is sent as the least significant
bit of timeslot of frame number 18.
4
Signaling Bit D
R/W
This bit is used to store Signaling Bit D that is sent as the least significant
bit of timeslot of frame number 24.
F
IGURE
93. T
IMING
D
IAGRAM
OF
THE
T
X
S
IG
_
N
I
NPUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
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