參數(shù)資料
型號: XRT86VL3x
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 82/153頁
文件大小: 1316K
代理商: XRT86VL3X
XRT86VL3X
75
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
Figure 83
shows the waveforms for connecting the Transmit non-multiplexed high-speed Input Interface block
to local Terminal Equipment.
Figure 84
shows the waveforms for connecting the Receive non-multiplexed
high-speed Input Interface block to local Terminal Equipment.
F
IGURE
82. R
ECEIVE
N
ON
-M
ULTIPLEXED
H
IGH
-S
PEED
C
ONNECTION
TO
LOCAL
TERMINAL
EQUIPMENT
USING
MVIP
2.048M
BIT
/
S
, 4.096M
BIT
/
S
,
OR
8.192M
BIT
/
S
F
IGURE
83. W
AVEFORMS
FOR
C
ONNECTING
THE
T
RANSMIT
N
ON
-M
ULTIPLEXED
H
IGH
-S
PEED
I
NPUT
I
NTERFACE
AT
MVIP 2.048M
BIT
/
S
, 4.096M
BIT
/
S
,
AND
8.192M
BIT
/
S
RxSERCLK0
RxSER0
RxMSYNC0
RxSYNC0
Receive
Payload
Data Input
Interface
Chn 0
Receive
Payload
Data Input
Interface
Chn N
Terminal
Equipment
XRT86VL3x
RxSERCLKn
RxSERn
RxMSYNCn
RxSYNCn
RxSERCLK = 2.048/4.096/8.192MHz
TxSERCLK
(1.5 MHz)
TxSERCLK (INV)
TxSER
TxSYNC(input)
TxCHCLK(INV)
TxCHN[0]/TxSig
TxCHN[1]/TxFrTD
F
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C
A B
D
Don't Care
C
A B
D
Don't Care
C
A B
D
Don't Care
Don't Care
C
A B
D
Don't Care
Note: The following signals are not aligned with the signals shown above. The TxTSClk is derived from 1.544MHz transmit clock.
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
TxMSYNC
(2/4/8MHz)
Don't Care
Don't care
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