參數(shù)資料
型號： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 37/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
30
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
3.9
Transmit SLC96 Data link Controller
The SLC96 T1 format is invented by AT&T and is used between the Digital Switch and a SLC96 formatted
remote terminal. The purpose of the SLC96 product is to provide standard telephone service or Plain Old
Telephone Service (POTS) in areas of high subscriber density but back-haul the traffic over T1 facilities.
To support the SLC96 formatted remote terminal equipment, which is likely in an underground location, the
T1 framer must:
Indicate equipment failures of the equipment to maintenance personal
Indicate failures of the POTS lines
Test the POTS lines
Provide redundancy on the T1s
The SLC96 framing format is a D4 Super-frame (SF) format with specialized data link information bits. These
data link information bits take the position of the Super-frame Alignment (Fs) bit positions. These bits consist of
the following.
Concentrator bits (C, bit position 1 to 11)
First Spoiler bits (FS, bit position 12 to 14)
Maintenance bits (M, bit position 15 to 17)
Alarm bits (A, bit position 18 to 19)
Protection Line Switch bits (S, bit position 20 to 23)
Second Spoiler bit (SS, bit position 24)
Resynchronization pattern (000111000111)
In SLC96 mode, a six 6-bit datalink message will generate a one 9-ms frame of the SLC96 message
format. The format of the datalink message is given in BELLCORE TR-TSY-000008. When SLC96 mode is
enabled, the Fs bit is replaced by the data link message read from memory at the beginning of each D4 super-
frame. The XRT86VL3x allocates two 6-byte buffers to provide the SLC96 Data Link Controller an alternating
access mechanism for information transmission. The bit ordering and usage is shown in the following table;
and the LSB is sent first. Note that these registers are memory-based storage and they need to be initialized.
Each register is read out of memory once every six SF super-frames. The memory holding these registers
owns a shared memory structure that is used by multiple devices. These include DS1 transmit module, DS1
receive module, Transmit LAPD Controller, Transmit SLC96 Data Link controller, Bit-Oriented Signaling
Processor, Receive LAPD Controller, Receive SLC96 Data Link Controller, Receive Bit-Oriented Signaling
Processor and microprocessor interface module.
T
ABLE
1: B
IT
O
RDERING
AND
U
SAGE
B
YTE
5
4
3
2
1
0
1
0
1
1
1
0
0
2
C1
1
1
1
0
0
3
C7
C6
C5
C4
C3
C2
4
1
0
C11
C10
C9
C8
5
A2
A1
M3
M2
M1
0
6
0
1
S4
S3
S2
S1
相關PDF資料
PDF描述
XRT86VL3X_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
相關代理商/技術參數(shù)
參數(shù)描述
XRT86VL3X_07 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VL3X_0710 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VX38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38_09 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
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