參數(shù)資料
型號: XRT86VL3x
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 69/153頁
文件大?。?/td> 1316K
代理商: XRT86VL3X
XRT86VL3X
62
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
Figure 67
shows the waveforms for connecting the Transmit non-multiplexed high-speed Input Interface block
to local Terminal Equipment.
Figure 68
shows the waveforms for connecting the Receive non-multiplexed
high-speed Input Interface block to local Terminal Equipment.
F
IGURE
67. W
AVEFORMS
FOR
C
ONNECTING
THE
T
RANSMIT
N
ON
-M
ULTIPLEXED
H
IGH
-S
PEED
I
NPUT
I
NTERFACE
AT
MVIP 2.048M
BIT
/
S
, 4.096M
BIT
/
S
,
AND
8.192M
BIT
/
S
F
IGURE
68. W
AVEFORMS
FOR
C
ONNECTING
THE
R
ECEIVE
N
ON
-M
ULTIPLEXED
H
IGH
-S
PEED
I
NPUT
I
NTERFACE
AT
MVIP 2.048M
BIT
/
S
, 4.096M
BIT
/
S
,
AND
8.192M
BIT
/
S
TxSERCLK
TxSERCLK (INV)
TxSER
TxSync(input)
TxSync(input)
MVIP mode
TxCHCLK
TxCHN[0]/TxSig
TxSyncFrd=0
TxCHN[1]/TxFrTD
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C
A B
D
Don't Care
C
A B
D
Don't Care
C
A B
D
Don't Care
C
A B
D
Don't Care
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
TxCHN[1]/TxFrTD
TxCHCLK
TxSyncFrd=1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C
A B
D
Don't Care
TxMsync
(2/4/8MHz)
RxSERCLK
RxSERCLK (INV)
RxSER
RxSync(input)
RxSync(input)
MVIP mode
RxCHCLK
RxCHN[0]/RxSig
RxSyncFrd=0
RxCHN[1]/RxFrTD
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C
A B
D
Don't Care
C
A B
D
Don't Care
C
A B
D
Don't Care
C
A B
D
Don't Care
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
Don't Care
8
7
6
5
4
3
2
1
RxCHN[1]/RxFrTD
RxCHCLK
RxSyncFrd=1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
C
A B
D
Don't Care
Timeslot 0
Timeslot 1
Timeslot 2
Timeslot 3
Timeslot 4
Timeslot 5
RxSERCLK
(2/4/8MHz)
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