- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376464 > XRT86VL3x (Exar Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 32/153頁(yè) |
| 文件大?。?/td> | 1316K |
| 代理商： | XRT86VL3X |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
XRT86VL3X
25
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
3.6
DS1/E1 Datalink Transmission Using the HDLC Controllers
The transmit framer block can insert data link information to outbound DS1/E1 frames. The data link
information can be inserted from the following sources.
Transmit Overhead Input Interface (TxOH)
Transmit HDLC1 Controller
Transmit Serial Input Interface (TxSER)
N
OTE
:
HDLC1 is the dedicated controller for transmission of LAPD messages through the datalink bits. If the datalink bits
are not used for LAPD messages, then HDLC1 can be used through the D/E time slots as with HDLC2 and HDLC3.
The Transmit Data Link Source Select bits within the Transmit Data Link Select Register (TSDLSR) determine
the source for the data link bits in ESF, SLC96, or T1DM for DS1 and CRC multi frame for E1. Each Transmit
HDLC Controller contains four major functional modules.
Bit-Oriented Signaling Processor
LAPD Controller
SLC96 Data Link Controller
Automatic Performance Report (APR) Generation
3.7
Transmit BOS (Bit Oriented Signaling) Processor
The Transmit BOS Processor handles transmission of BOS messages through the data link channel. The
processor can be set for a specific amount of repetitions a certain BOS message will be transmitted, or it may
be placed in an infinite loop. The processor can also insert a BOS IDLE flag sequence and/or an ABORT
sequence to be transmitted on the data link channel.
3.7.1
Description of BOS
Bit-Oriented Signaling messages are a 16-bit pattern of which a 6-bit message is embedded as shown in the
following table.
Where D5 is the MSB and D0 is the LSB. The rightmost "1" is transmitted first. BOS is classified into the
following two groups.
Priority Codeword Message
Command and Response Information
3.7.2
Priority Codeword Message
A Priority Codeword Message is preemptive and has the highest priority among all data link information. A
Priority Codeword indicates a condition that is affecting the quality of service and thus shall be transmitted until
the condition no longer exists. The duration of transmission should not be less than one second. A priority
codeword may be interrupted by software for 100 milliseconds to send maintenance commands with a
minimum interval of one second between interruptions. Yellow alarm (00000000 11111111) is the only priority
message defined in industry standards.
3.7.3
Command and Response Information
Command and Response Information is transmitted to perform various functions. The BOS Processor can
send a command and response by transmitting a minimum of 10 repetitions of the appropriate codeword
pattern. A Command and response data transmission initiates action at the remote end, while the remote end
will respond by sending Bit-Oriented response message to acknowledge the received commands. The
activation and deactivation of line remote loop-back and local payload loop-back functions are of this type.
BOS M
ESSAGE
F
ORMAT
0
D5
D4
D3
D2
D1
D0
0
1
1
1
1
1
1
1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。