- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376464 > XRT86VL3x (Exar Corporation) Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 PDF資料下載
參數(shù)資料
| 型號： | XRT86VL3x |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 7/153頁 |
| 文件大小： | 1316K |
| 代理商： | XRT86VL3X |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁
XRT86VL3X
IV
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL3x N-Channel DS1 (T1/E1/J1) Framer/LIU Combo ........................................................................... 1
Figure 2.: LIU Transmit Connection Diagram Using Internal Termination ......................................................................... 4
Figure 3.: LIU Receive Connection Diagram Using Internal Termination ......................................................................... 4
Figure 4.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ............................................ 5
Figure 5.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy ............................................. 6
Figure 6.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ................................................................. 7
Figure 7.: Transmit T1/E1 Serial PCM Interface ................................................................................................................ 8
Figure 8.: Receive T1/E1 Serial PCM Interface ................................................................................................................. 8
Figure 9.: T1 Fractional Interface ....................................................................................................................................... 9
Figure 10.: T1/E1 Time Slot Substitution and Control ..................................................................................................... 10
Figure 11.: Robbed Bit Signaling / CAS Signaling ........................................................................................................... 11
Figure 12.: ESF / CAS External Signaling Bus ................................................................................................................ 11
Figure 13.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus .......................................................12
Figure 14.: T1/E1 Overhead Interface ............................................................................................................................. 12
Figure 15.: T1 External Overhead Datalink Bus .............................................................................................................. 13
Figure 16.: E1 Overhead External Datalink Bus .............................................................................................................. 13
Figure 17.: Simplified Block Diagram of the Framer Bypass Mode ................................................................................. 14
Figure 18.: T1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 19.: E1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 20.: Transmit High-Speed Bit Multiplexed Block Diagram .................................................................................... 16
Figure 21.: Receive High-Speed Bit Multiplexed Block Diagram ..................................................................................... 16
Figure 22.: Simplified Block Diagram of Local Analog Loopback .................................................................................... 17
Figure 23.: Simplified Block Diagram of Remote Loopback ............................................................................................ 17
Figure 24.: Simplified Block Diagram of Digital Loopback ............................................................................................... 18
Figure 25.: Simplified Block Diagram of Dual Loopback .................................................................................................. 18
Figure 26.: Simplified Block Diagram of the Framer Remote Line Loopback .................................................................. 19
Figure 27.: Simplified Block Diagram of the Framer Local Loopback .............................................................................. 19
Figure 28.: HDLC Controllers .......................................................................................................................................... 20
Figure 29.: Storing and Retrieving Message Contents .................................................................................................... 21
Figure 30.: Sending HDLC Messages ............................................................................................................................. 22
Figure 31.: Receiving HDLC Messages ........................................................................................................................... 23
Figure 32.: Receive HDLC Event Timing .........................................................................................................................24
Figure 33.: LAPD Frame Structure .................................................................................................................................. 27
Figure 34.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86VL3x ....................................... 33
Figure 35.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ............................................ 35
Figure 36.: DS1 Transmit Overhead Input Timing in N or SLC96 Framing Format Mode ............................................ 36
Figure 37.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ........................................ 36
Figure 38.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86VL3x ...........................................37
Figure 39.: DS1 Receive Overhead Output Interface module in ESF framing format mode ...........................................39
Figure 40.: DS1 Receive Overhead Output Interface Timing in N or SLC96 Framing Format mode ........................... 40
Figure 41.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode ....................................... 41
Figure 42.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86VL3x ................................................42
Figure 43.: E1 Transmit Overhead Input Interface Timing ............................................................................................... 44
Figure 44.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86VL3x .............................................. 45
Figure 45.: E1 Receive Overhead Output Interface Timing ............................................................................................. 46
Figure 46.: TAOS (Transmit All Ones) ............................................................................................................................. 47
Figure 47.: Simplified Block Diagram of the ATAOS Function ......................................................................................... 47
Figure 48.: Network Loop Up Code Generation .............................................................................................................. 48
Figure 49.: Network Loop Down Code Generation .......................................................................................................... 48
Figure 50.: Long Haul Line Build Out with -7.5dB Attenuation ........................................................................................ 49
Figure 51.: Long Haul Line Build Out with -15dB Attenuation ......................................................................................... 49
Figure 52.: Long Haul Line Build Out with -22.5dB Attenuation ...................................................................................... 50
Figure 53.: Arbitrary Pulse Segment Assignment ............................................................................................................ 51
Figure 54.: Typical Connection Diagram Using Internal Termination .............................................................................. 52
Figure 55.: Typical Connection Diagram Using Internal Termination .............................................................................53
Figure 56.: Simplified Block Diagram of the Equalizer and Peak Detector ......................................................................54
Figure 57.: Simplified Block Diagram of the Cable Loss Indicator ................................................................................... 54
Figure 58.: Test Configuration for Measuring Receive Sensitivity ................................................................................... 55
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL3X_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL3X | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT91L30_0611 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L306 | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L30IQ | STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL3X_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VL3X_0710 | 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION |
| XRT86VX38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
| XRT86VX38_09 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION |
| XRT86VX38_0906 | 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。