參數(shù)資料
型號： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 125/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
118
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
10.4
T1 Super Frame Format (SF)
The Superframe Format (SF), is also referred to as the D4 format. The requirement for associated signaling in
frames 6 and 12 dictates that the frames be distinguishable. This leads to a multiframe structure consisting of
12 frames per superframe (SF) as shown in
Figure 107
and
Table 10
. This structure of frames and
multiframes is defined by the F-bit pattern. The F-bit is designated alternately as an Ft bit (terminal framing bit)
or Fs bit (signalling framing bit). The Ft bit carries a pattern of alternating zeros and ones (101010) in odd
frames that defines the boundaries so that one timeslot may be distinguished from another. The Fs bit carries
a pattern of (001110) in even frames and defines the multiframe boundaries so that one frame may be
distinguished from another.
F
IGURE
107. T1 S
UPERFRAME
PCM F
ORMAT
T
ABLE
10: S
UPERFRAME
F
ORMAT
F
RAME
B
IT
F-B
ITS
B
IT
U
SE
IN
E
ACH
T
IMESLOT
S
IGNALLING
C
HANNEL
T
ERMINAL
F
RAMING
F
T
T
ERMINAL
F
RAMING
F
S
T
RAFFIC
S
IG
1
0
1
----
1-8
----
----
2
193
----
0
1-8
----
----
3
386
0
----
1-8
----
----
4
579
----
0
1-8
----
----
5
772
1
----
1-8
----
----
6
965
----
1
1-7
8
A
7
1158
0
----
1-8
----
----
8
1351
----
1
1-8
----
----
B
A
Bit 0 Bit 1
Bit 2 Bit 3
Bit 4 Bit 5 Bit 6
Bit 7
8 Bits per Timeslot
Ft
or
Fs
Ft
or
Fs
TS
1
TS
1
TS
2
TS
2
------------------
------------------
TS
13
TS
13
-------------------
-------------------
TS
24
TS
24
FR
1
FR
1
FR
2
FR
2
------------------
------------------
FR
7
FR
7
-------------------
-------------------
FR
11
FR
11
FR
12
FR
12
Signalling nformation
Bit 7
During:
Frame 12
Frame 6
24 Timeslots per Frame
Frame = 193 Bits
Multiframe
SF = 12 Frames
相關(guān)PDF資料
PDF描述
XRT86VL3X_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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