參數(shù)資料
型號(hào)： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 5/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
II
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
4.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA
LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ................................................................................................. 33
4.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC96 FRAMING FORMAT MODE .......................................................................... 35
4.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-
NALING (R) BITS IN T1DM FRAMING FORMAT MODE ............................................................................................. 36
4.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ........................................................................... 37
4.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 37
4.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY
DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ...................................................................................... 37
4.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC96 FRAMING FORMAT MODE .......................................................................... 39
4.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE
SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ....................................................................................... 40
4.3 E1 OVERHEAD INTERFACE BLOCK .............................................................................................................. 41
4.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................... 41
4.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................... 41
4.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-
QUENCE IN E1 FRAMING FORMAT MODE ................................................................................................................ 42
4.5 E1 RECEIVE OVERHEAD INTERFACE ........................................................................................................... 45
4.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ................................................. 45
4.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT
SEQUENCE IN E1 FRAMING FORMAT MODE ............................................................................................................ 45
5.0 LIU TRANSMIT PATH ...........................................................................................................................47
5.1 TRANSMIT DIAGNOSTIC FEATURES ............................................................................................................. 47
5.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................... 47
5.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ........................................................................................................... 47
5.1.3 NETWORK LOOP UP CODE ........................................................................................................................................ 47
5.1.4 NETWORK LOOP DOWN CODE ................................................................................................................................. 48
5.1.5 QRSS GENERATION .................................................................................................................................................... 48
5.2 T1 LONG HAUL LINE BUILD OUT (LBO) ........................................................................................................48
5.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ...................................................................................................... 51
5.3.1 ARBITRARY PULSE GENERATOR ............................................................................................................................. 51
5.3.2 DMO (DIGITAL MONITOR OUTPUT) ........................................................................................................................... 52
5.3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................................. 52
5.4 LINE TERMINATION (TTIP/TRING) .................................................................................................................. 52
6.0 LIU RECEIVE PATH ..............................................................................................................................53
6.1 LINE TERMINATION (RTIP/RRING) ................................................................................................................. 53
6.1.1 INTERNAL TERMINATION ........................................................................................................................................... 53
6.1.2 EQUALIZER CONTROL ............................................................................................................................................... 53
6.1.3 CABLE LOSS INDICATOR ........................................................................................................................................... 54
6.2 RECEIVE SENSITIVITY ..................................................................................................................................... 54
6.2.1 AIS (ALARM INDICATION SIGNAL) ............................................................................................................................ 55
6.2.2 NLCD (NETWORK LOOP CODE DETECTION) ........................................................................................................... 55
6.2.3 FLSD (FIFO LIMIT STATUS DETECTION) .................................................................................................................. 56
6.2.4 RECEIVE JITTER ATTENUATOR ................................................................................................................................ 56
6.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ..................................................................................................... 56
7.0 THE E1 TRANSMIT/RECEIVE FRAMER ..............................................................................................58
7.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK .................... 58
7.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
XRT84V24 COMPATIBLE 2.048MBIT/S MODE ........................................................................................................... 58
7.2 TRANSMIT/RECEIVE HIGH-SPEED BACK-PLANE INTERFACE .................................................................. 60
7.2.1 NON-MULTIPLEXED HIGH-SPEED MODE ................................................................................................................. 60
7.2.2 MULTIPLEXED HIGH-SPEED MODE .......................................................................................................................... 63
7.3 BRIEF DISCUSSION OF COMMON CHANNEL SIGNALING IN E1 FRAMING FORMAT .............................. 69
7.4 BRIEF DISCUSSION OF CHANNEL ASSOCIATED SIGNALING IN E1 FRAMING FORMAT ....................... 69
7.5 INSERT/EXTRACT SIGNALING BITS FROM TSCR REGISTER .................................................................... 69
7.6 INSERT/EXTRACT SIGNALING BITS FROM TXCHN[0]_N/TXSIG PIN ......................................................... 69
7.7 ENABLE CHANNEL ASSOCIATED SIGNALING AND SIGNALING DATA SOURCE CONTROL ................. 70
8.0 THE DS1 TRANSMIT/RECEIVE FRAMER ............................................................................................71
8.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK .................... 71
8.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
1.544MBIT/S MODE ....................................................................................................................................................... 71
8.2 TRANSMIT/RECEIVE HIGH-SPEED BACK-PLANE INTERFACE .................................................................. 73
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