參數(shù)資料
型號： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 48/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
41
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
Figure 41
below shows the timing diagram of the output signals associated with the DS1 Receive Overhead
Output Interface module in T1DM framing format mode.
4.3
E1 Overhead Interface Block
The XRT86VL3x has the ability to extract or insert E1 data link information from or into the E1 National bit
sequence. The source and destination of these inserted and extracted data link bits would be from either the
internal HDLC Controller or the external device accessible through E1 Overhead Interface Block. The
operation of the Transmit Overhead Input Interface Block and the Receive Overhead Output Interface Block
will be discussed separately.
4.4
E1 Transmit Overhead Input Interface Block
4.4.1
Description of the E1 Transmit Overhead Input Interface Block
The E1 Transmit Overhead Input Interface Block will allow an external device to be the provider of the E1
National bit sequence. This interface provides interface signals and required interface timing to shift in proper
data link information at proper time.
The Transmit Overhead Input Interface for a given Framer consists of two signals.
TxOHClk_n: The Transmit Overhead Input Interface Clock Output signal
TxOH_n: The Transmit Overhead Input Interface Input signal.
The Transmit Overhead Input Interface Clock Output pin (TxOHCLK_n) generates a rising clock edge for each
National bit that is configured to carry Data Link information according to setting of the framer. The Data Link
equipment interfaced to the Transmit Overhead Input Interface should update the data link bits on the TxOH_n
line upon detection of the rising edge of TxOHClk_n. The Transmit Overhead Input Interface block will sample
and latch the data link bits on the TxOH_n line on the falling edge of TxOHClk_n. The data link bits will be
included in and transmitted via the outgoing E1 frames.
The figure below shows block diagram of the DS1 Transmit Overhead Input Interface of XRT86VL3x.
F
IGURE
41. DS1 R
ECEIVE
O
VERHEAD
O
UTPUT
I
NTERFACE
T
IMING
IN
T1DM F
RAMING
F
ORMAT
MODE
相關(guān)PDF資料
PDF描述
XRT86VL3X_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
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參數(shù)描述
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XRT86VL3X_0710 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
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XRT86VX38_09 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
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