參數(shù)資料
型號(hào)： XRT86VL3x
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 36/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X
XRT86VL3X
29
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
REV. 1.2.2
3.8.10
Service Access Point Identifier (SAPI)
The Service Access Point Identifier identifies a point at which data link layer services are preceded by a data
link layer entity type to a layer 3 or management entity. Consequently, the SAPI specifies a data link layer entity
type that should process a data link layer frame and also a layer 3 or management entity, which is to receive
information carried by the data link layer frame. The SAPI allows 64 service access points to be specified,
where bit 3 of the address field octet containing the SAPI is the least significant binary digit and bit 8 is the most
significant. SAPI values are 0x14 and 0x15 for performance report message and path or test signal
identification message respectively.
3.8.11
Terminal Endpoint Identifier (TEI)
The TEI sub-field allows 128 values where bit 2 of the address field octet containing the TEI is the least
significant binary digit and bit 8 is the most significant binary digit. The TEI sub-field bit pattern 111 1111 (=127)
is defined as the group TEI. The group TEI is assigned permanently to the broadcast data link connection
associated with the addressed Service Access Point (SAP). TEI values other than 127 are used for the point-
to-point data link connections associated with the addressed SAP. Non-automatic TEI values (0-63) are
selected by the user, and their allocation is the responsibility of the user. The network automatically selects
and allocates TEI values (64-126).
3.8.12
Control Field
The control field identifies the type of frame which will be either a command or response. The control field shall
consist of one or two octets. Three types of control field formats are specified: 2-octet numbered information
transfer (I format), 2-octet supervisory functions (S format), and single-octet unnumbered information transfers
and control functions (U format). The control field for T1/E1 message is categorized as a single-octet
unacknowledged information transfer having the value 0x03.
3.8.13
Frame Check Sequence (FCS) Field
The source of either the performance report or an identification message shall generate the frame check
sequence. The FCS field shall be a 16-bit sequence. It shall be the ones complement of the sum (modulo 2)
of:
The remainder of xk (x15 + x14 + x13 + x12 + x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + x3 + x2 + x + 1)
divided (modulo 2) by the generator polynomial x16 + x12 + x5 + 1, where k is the number of bits in the frame
existing between, but not including, the final bit of the opening flag and the first bit of the FCS, excluding bits
inserted for transparency, and
The remainder of the division (modulo 2) by the generator polynomial x16 + x12 + x5 + 1, of the product of
x16 by the content of the frame existing between, but not including, the final bit of the opening flag and the
first bit of the FCS, excluding bits inserted for transparency.
As a typical implementation at the transmitter, the initial content of the register of the device computing the
remainder of the division is preset to all 1s and is then modified by division by the generator polynomial on the
address, control and information fields; the ones complement of the resulting remainder is transmitted as the
16-bit FCS.
As a typical implementation at the receiver, the initial content of the register of the device computing the
remainder is preset to all 1s. The final remainder, after multiplication by x16 and then division (modulo 2) by the
generator polynomial x16 + x12 + x5 + 1 of the serial incoming protected bits and the FCS, will be
0001110100001111 (x15 through x0, respectively) in the absence of transmission errors.
3.8.14
Transparency (Zero Stuffing)
A transmitting data link layer entity shall examine the frame content between the opening and closing flag
sequences, (address, control, information and FCS field) and shall insert a 0 bit after all sequences of five
contiguous 1 bits (including the last five bits of the FCS) to ensure that an IDLE flag or an Abort sequence is
not simulated within the frame. A receiving data link layer entity shall examine the frame contents between the
opening and closing flag sequences and shall discard any 0 bit which directly follows five contiguous 1 bits.
相關(guān)PDF資料
PDF描述
XRT86VL3X_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL3X_07 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VL3X_0710 制造商:EXAR 制造商全稱:EXAR 功能描述:T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
XRT86VX38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38_09 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
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