參數(shù)資料
型號(hào): XC3S1000-4VQG100C
廠商: XILINX INC
元件分類: FPGA
英文描述: Spartan-3 FPGA Family: Complete Data Sheet
中文描述: FPGA, 192 CLBS, 50000 GATES, PQFP100
封裝: LEAD FREE, VQFP-100
文件頁(yè)數(shù): 87/198頁(yè)
文件大?。?/td> 1605K
代理商: XC3S1000-4VQG100C
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)當(dāng)前第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)
DS099-4 (v1.6) January 17, 2005
Preliminary Product Specification
www.xilinx.com
1
2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Introduction
This data sheet module describes the various pins on a
Spartan-3 FPGA and how they connect to the supported
component packages.
The
Pin Types
section categorizes all of the FPGA
pins by their function type.
The
Pin Definitions
section provides a top-level
description for each pin on the device.
The
Detailed, Functional Pin Descriptions
section
offers significantly more detail about each pin,
especially for the dual- or special-function pins used
during device configuration.
Some pins have associated 4 behavior, controlled by
settings in the configuration bitstream. These options
are described in the
Bitstream Options
section.
The
Package Overview
section describes the various
packaging options available for Spartan-3 FPGAs.
Detailed pin list tables and footprint diagrams are
provided for each package solution.
Pin Descriptions
Pin Types
A majority of the pins on a Spartan-3 FPGA are gen-
eral-purpose, user-defined I/O pins. There are, however, up
to 12 different functional types of pins on Spartan-3 pack-
ages, as outlined in
Table 1
. In the package footprint draw-
ings that follow, the individual pins are color-coded
according to pin type as in the table.
0112
Spartan-3 FPGA Family:
Pinout Descriptions
DS099-4 (v1.6) January 17, 2005
0
0
Product Specification
R
Table 1:
Types of Pins on Spartan-3 FPGAs
Type/
Color
Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be
paired together to form differential I/Os.
IO,
IO_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the
configuration process and then usually available as a user I/O
after configuration. If the pin is not used during configuration, this
pin behaves as an I/O-type pin. There are 12 dual-purpose
configuration pins on every package.
IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,
IO_Lxxy_#/D2, IO_Lxxy_#/D3,
IO_Lxxy_#/D4, IO_Lxxy_#/D5,
IO_Lxxy_#/D6, IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B, IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY/DOUT,
IO_Lxxy_#/INIT_B
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin.
Every package has seven dedicated configuration pins. These
pins are powered by VCCAUX.
CCLK, DONE, M2, M1, M0, PROG_B,
HSWAP_EN
JTAG
Dedicated JTAG pin. Not available as a user-I/O pin. Every
package has four dedicated JTAG pins. These pins are powered
by VCCAUX.
TDI, TMS, TCK, TDO
DCI
Dual-purpose pin that is either a user-I/O pin or used to calibrate
output buffer impedance for a specific bank using Digital
Controlled Impedance (DCI). There are two DCI pins per I/O
bank.
IO/VRN_#
IO_Lxxy_#/VRN_#
IO/VRP_#
IO_Lxxy_#/VRP_#
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all
other VREF pins in the same bank, provides a reference voltage
input for certain I/O standards. If used for a reference voltage
within a bank, all VREF pins within the bank must be connected.
IO/VREF_#
IO_Lxxy_#/VREF_#
相關(guān)PDF資料
PDF描述
XC3S1000-4VQG100I Spartan-3 FPGA Family: Complete Data Sheet
XC3S1000-5CP132C Spartan-3 FPGA Family: Complete Data Sheet
XC3S1000-5CP132I Spartan-3 FPGA Family: Complete Data Sheet
XC4000A LAMP
XC4002A Logic Cell Array Family
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S1000-4VQG100I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet
XC3S1000-5CP132C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA
XC3S1000-5CP132I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA
XC3S1000-5CPG132C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet
XC3S1000-5CPG132I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet