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參數(shù)資料
| 型號： | XC3S1000-4VQG100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP100 |
| 封裝： | LEAD FREE, VQFP-100 |
| 文件頁數(shù)： | 16/198頁 |
| 文件大小： | 1605K |
| 代理商： | XC3S1000-4VQG100C |
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Spartan-3 FPGA Family: Functional Description
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
www.xilinx.com
9
R
4.
If none of the standards assigned to the I/Os of the
(interconnected) bank(s) use V
CCO
, tie all associated
V
CCO
lines to 2.5V.
In general, apply 2.5V to V
CCO
Bank 4 from power-on to
the end of configuration. Apply the same voltage to
V
CCO
Bank 5 during parallel configuration or a
Readback operation. For information on how to
program the FPGA using 3.3V signals and power, see
the
3.3V-Tolerant Configuration Interface
section.
If any of the standards assigned to the Inputs of the bank
use V
REF
, then observe the following additional rules:
1.
Leave no V
REF
pins unconnected on any bank.
2.
Set all V
REF
lines associated with the bank to the same
voltage level.
3.
The V
REF
levels used by all standards assigned to the
Inputs of the bank must agree. The Xilinx development
software checks for this. Tables
4
and
6
describe how
different standards use the V
REF
supply.
If none of the standards assigned to the Inputs of a bank
use V
REF
for biasing input switching thresholds, all associ-
ated V
REF
pins function as User I/Os.
5.
Exceptions to Banks Supporting I/O
Standards
Bank 5 of any Spartan-3 device in a VQ100 or TQ144 pack-
age does not support DCI signal standards. In this case,
bank 5 has neither VRN nor VRP pins.
Furthermore, banks 4 and 5 of any Spartan-3 device in a
VQ100 package do not support signal standards using
V
REF
(see
Table 4
). In this case, the two banks do not have
any V
REF
pins.
Supply Voltages for the IOBs
Three different supplies power the IOBs:
1.
The V
CCO
supplies, one for each of the FPGA’s I/O
banks, power the output drivers, except when using the
GTL and GTLP signal standards. The voltage on the
V
CCO
pins determines the voltage swing of the output
signal.
2.
V
CCINT
is the main power supply for the FPGA’s internal
logic.
3.
The V
CCAUX
is an auxiliary source of power, primarily to
optimize the performance of various FPGA functions
such as I/O switching.
The I/Os During Power-On, Configuration, and
User Mode
With no power applied to the FPGA, all I/Os are in a
high-impedance state. The V
CCINT
(1.2V), V
CCAUX
(2.5V),
and V
CCO
supplies may be applied in any order. Before
power-on can finish, V
CCINT
, V
CCO
Bank 4, and V
CCAUX
must have reached their respective minimum recom-
mended operating levels (see
Table 2
in Module 3:
DC and
Switching Characteristics
). At this time, all I/O drivers
also will be in a high-impedance state. V
CCO
Bank 4,
V
CCINT
, and V
CCAUX
serve as inputs to the internal
Power-On Reset circuit (POR).
A Low level applied to the HSWAP_EN input enables
pull-up resistors on User I/Os from power-on throughout
configuration. A High level on HSWAP_EN disables the
pull-up resistors, allowing the I/Os to float. As soon as
power is applied, the FPGA begins initializing its configura-
tion memory. At the same time, the FPGA internally asserts
the Global Set-Reset (GSR), which asynchronously resets
all IOB storage elements to a Low state.
Upon the completion of initialization, INIT_B goes High,
sampling the M0, M1, and M2 inputs to determine the con-
figuration mode. At this point, the configuration data is
loaded into the FPGA. The I/O drivers remain in a
high-impedance state (with or without pull-up resistors, as
determined by the HSWAP_EN input) throughout configura-
tion.
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the begin-
ning of design operation in the User mode. At this point,
those I/Os to which signals have been assigned go active
while all unused I/Os remain in a high-impedance state. The
release of the GSR net, also part of Start-up, leaves the IOB
registers in a Low state by default, unless the loaded design
reverses the polarity of their respective RS inputs.
In User mode, all internal pull-up resistors on the I/Os are
disabled and HSWAP_EN becomes a “don’t care” input. If it
is desirable to have pull-up or pull-down resistors on I/Os
carrying signals, the appropriate symbol — e.g., PULLUP,
PULLDOWN — must be placed at the appropriate pads in
the design. The Bitstream Generator (Bitgen) option
UnusedPin available in the Xilinx development software
determines whether unused I/Os collectively have pull-up
resistors, pull-down resistors, or no resistors in User mode.
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