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參數(shù)資料
| 型號(hào)： | XC3S1000-4VQG100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PQFP100 |
| 封裝： | LEAD FREE, VQFP-100 |
| 文件頁(yè)數(shù)： | 55/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-4VQG100C |
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Spartan-3 FPGA Family: DC and Switching Characteristics
8
www.xilinx.com
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
R
LVCMOS33
(4)
2
4
6
8
2
4
6
8
–2
–4
–6
–8
–12
–16
–24
Note 3
0.4
V
CCO
- 0.4
12
16
24
12
16
24
LVDCI_33,
LVDCI_DV2_33
LVTTL
(4)
Note 3
2
4
6
8
2
4
6
8
–2
–4
–6
–8
–12
–16
–24
Note 6
–6.7
Note 3
–8.1
Note 3
–16.2
Note 3
0.4
2.4
12
16
24
12
16
24
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL2_I
SSTL2_I_DCI
SSTL2_II
(7)
SSTL2_II_DCI
(7)
Notes:
1.
The numbers in this table are based on the conditions set forth in
Table 5
and
Table 8
.
2.
Descriptions of the symbols used in this table are as follows:
I
OL
-- the output current condition under which V
OL
is tested
I
OH
-- the output current condition under which V
is tested
V
OL
-- the output voltage that indicates a Low logic level
V
OH
-- the output voltage that indicates a High logic level
V
IL
-- the input voltage that indicates a Low logic level
V
IH
-- the input voltage that indicates a High logic level
V
CCO
-- the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
V
REF
-- the reference voltage for setting the input switching threshold
V
TT
-- the voltage applied to a resistor termination
3.
Tested according to the standard’s relevant specifications. When using the DCI version of a standard on a given I/O bank, that bank
will consume more power than if the non-DCI version had been used instead. The additional power is drawn for the purpose of
impedance-matching at the I/O pins. A portion of this power is dissipated in the two R
REF
resistors.
4.
For the LVCMOS and LVTTL standards: the same V
OL
and V
OH
limits apply for both the Fast and Slow slew attributes.
5.
All Dedicated output pins (CCLK, DONE, and TDO) as well as Dual-Purpose totem-pole output pins (D0-D7 and BUSY/DOUT)
exhibit the characteristics of LVCMOS25 with 12 mA drive and Fast slew rate. For information concerning the use of 3.3V signals,
see the
3.3V-Tolerant Configuration Interface
section in Module 2:
Functional Description
.
6.
Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference
Design" (
XAPP653
).
7.
The minimum usable V
TT
voltage is 1.25V.
Note 6
6.7
Note 3
8.1
Note 3
16.2
Note 3
0.10V
CCO
V
TT
- 0.475
0.90V
CCO
V
TT
+ 0.475
V
TT
- 0.61
V
TT
+ 0.61
V
TT
- 0.80
V
TT
+ 0.80
Table 9:
DC Characteristics of User I/Os Using Single-Ended Standards
(Continued)
Signal Standard and Current
Drive Attribute (mA)
Test Conditions
Logic Level Characteristics
V
OL
Max (V)
I
OL
(mA)
I
OH
(mA)
V
OH
Min (V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4VQG100I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC4000A | LAMP |
| XC4002A | Logic Cell Array Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4VQG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CP132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CPG132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CPG132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
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