- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄231501 > W972GG8JB-25 (WINBOND ELECTRONICS CORP) 256M X 8 DDR DRAM, 0.4 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | W972GG8JB-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁數(shù)： | 46/86頁 |
| 文件大?。?/td> | 1466K |
| 代理商： | W972GG8JB-25 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 50 -
Revision A02
25.
New units, tCK(avg) and nCK, are introduced in DDR2-667, DDR2-800 and DDR2-1066.
Unit tCK(avg) represents the actual tCK(avg) of the input clock under operation.
Unit nCK represents one clock cycle of the input clock, counting the actual clock edges.
Examples:
For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min.
26. These parameters are measured from a command/address signal (CKE,
CS , RAS , CAS , WE , ODT, BA0, A0, A1, etc.)
transition edge to its respective clock signal (CLK/
CLK ) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
27. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can
be executed.
28. These parameters are measured from a data strobe signal (DQS,
DQS , RDQS, RDQS ) crossing to its respective clock
signal (CLK/
CLK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc),
etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is
present or not.
29. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe
signal (DQS,
DQS , RDQS, RDQS ) crossing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WF512K32-150CJC | 512K X 32 FLASH 5V PROM MODULE, 150 ns, CQCC68 |
| W73B586A-09L | 32K X 18 CACHE SRAM, 9 ns, PQCC52 |
| WS512K32-100G4TM | 2M X 8 MULTI DEVICE SRAM MODULE, 100 ns, CQFP68 |
| WS512K32-35G4M | 2M X 8 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
| WS512K32-35G4Q | 2M X 8 MULTI DEVICE SRAM MODULE, 35 ns, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W972GG8JB-25I | 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA |
| W972GG8JB-3 | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS |
| W9751G6IB-25 | 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W9751G6JB | 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM |
| W9751G6JB-25 | 制造商:Winbond Electronics Corp 功能描述:512GB DDRII |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。