參數(shù)資料
型號： W972GG8JB-25
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 256M X 8 DDR DRAM, 0.4 ns, PBGA60
封裝： 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60
文件頁數(shù)： 40/86頁
文件大?。?/td> 1466K
代理商： W972GG8JB-25
W972GG8JB
Publication Release Date: Feb. 18, 2011
- 45 -
Revision A02
9.11.2 AC Characteristics and Operating Condition for -25/25I/-3 speed grades
SYM.
SPEED GRADE
DDR2-800 (-25/25I)
DDR2-667 (-3)
UNITS
25 NOTES
Bin(CL-tRCD-tRP)
5-5-5/6-6-6
5-5-5
PARAMETER
MIN.
MAX.
MIN.
MAX.
tRCD
Active to Read/Write Command Delay Time
12.5
15
nS
23
tRP
Precharge to Active Command Period
12.5
15
nS
23
tRC
Active to Ref/Active Command Period
57.5
60
nS
23
tRAS
Active to Precharge Command Period
45
70000
45
70000
nS
4,23
tRFC
Auto Refresh to Active/Auto Refresh command
period
195
195
nS
5
tREFI
Average periodic
refresh Interval
-40°C
≤ TCASE ≤ 85°C
7.8
7.8
μS
5
85°C
< TCASE
≤ 95°C
3.9
3.9
μS
5,6
tCCD
CAS to CAS command delay
2
2
nCK
tCK(avg)
Average clock period
tCK(avg) @ CL=3
5
8
5
8
nS
30,31
tCK(avg) @ CL=4
3.75
8
3.75
8
nS
30,31
tCK(avg) @ CL=5
2.5
8
3
8
nS
30,31
tCK(avg) @ CL=6
2.5
8
nS
30,31
tCH(avg)
Average clock high pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tCL(avg)
Average clock low pulse width
0.48
0.52
0.48
0.52
tCK(avg)
30,31
tAC
DQ output access time from CLK/
CLK
-400
400
-450
450
pS
35
tDQSCK
DQS output access time from CLK /
CLK
-350
350
-400
400
pS
35
tDQSQ
DQS-DQ skew for DQS & associated DQ signals
200
240
pS
13
tCKE
CKE minimum high and low pulse width
3
3
nCK
7
tRRD
Active to active command period for 1KB page
size
7.5
7.5
nS
8,23
tFAW
Four Activate Window for 1KB page size
35
37.5
nS
23
tWR
Write recovery time
15
15
nS
23
tDAL
Auto-precharge write recovery + precharge time
WR + tnRP
WR + tnRP
nCK
24
tWTR
Internal Write to Read command delay
7.5
7.5
nS
9,23
tRTP
Internal Read to Precharge command delay
7.5
7.5
nS
4,23
tIS (base)
Address and control input setup time
175
200
pS
10,26,
40,42,43
tIH (base)
Address and control input hold time
250
275
pS
11,26,
40,42,43
tIS (ref)
Address and control input setup time
375
400
pS
10,26,
40,42,43
tIH (ref)
Address and control input hold time
375
400
pS
11,26,
40,42,43
tIPW
Address and control input pulse width for each
input
0.6
0.6
tCK(avg)
tDQSS
DQS latching rising transitions to associated
clock edges
-0.25
0.25
-0.25
0.25
tCK(avg)
28
tDSS
DQS falling edge to CLK setup time
0.2
0.2
tCK(avg)
28
tDSH
DQS falling edge hold time from CLK
0.2
0.2
tCK(avg)
28
tDQSH
DQS input high pulse width
0.35
0.35
tCK(avg)
tDQSL
DQS input low pulse width
0.35
0.35
tCK(avg)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W972GG8JB-25I 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 2.5NS 80WBGA
W972GG8JB-3 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 2G-Bit 256Mx8 1.8V 60-Pin WBGA 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 2GBIT 3NS
W9751G6IB-25 功能描述:IC DDR2-800 SDRAM 512MB 84-WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR)
W9751G6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 4 BANKS ? 16 BIT DDR2 SDRAM
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