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| 型號： | W972GG8JB-25 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 11 X 11.50 MM, ROHS COMPLIANT, WBGA-60 |
| 文件頁數(shù)： | 36/86頁 |
| 文件大?。?/td> | 1466K |
| 代理商： | W972GG8JB-25 |
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W972GG8JB
Publication Release Date: Feb. 18, 2011
- 41 -
Revision A02
IDD4R
Operating Burst Read Current
All banks open, Continuous burst reads, IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH,
CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
165
135
120
mA
1,2,3,4,5,
6
IDD4W
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH,
CS is HIGH between valid commands;
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
145
120
110
mA
1,2,3,4,5,
6
IDD5B
Burst Refresh Current
tCK = tCK(IDD);
Refresh command every tRFC = tRFC(IDD) interval;
CKE is HIGH,
CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
175
160
150
mA
1,2,3,4,5,
6
IDD5D
Distributed Refresh Current
tCK = tCK(IDD);
Refresh command every tREFI =
7.8 μS interval;
CKE is LOW,
CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
16
mA
1,2,3,4,5,
6
IDD6
Self Refresh Current
CKE
≤ 0.2 V, external clock off, CLK and CLK at 0 V;
Other control and address inputs are FLOATING;
Data bus inputs are FLOATING. (TCASE
≤ 85°C)
12
mA
1,2,3,4,5,
6,7
IDD7
Operating Bank Interleave Read Current
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD
= tRCD(IDD);
CKE is HIGH,
CS is HIGH between valid commands;
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
220
200
180
mA
1,2,3,4,5,
6
Notes:
1. VDD = 1.8 V
0.1V; VDDQ = 1.8 V 0.1V.
2. IDD specifications are tested after the device is properly initialized.
3. Input slew rate is specified by AC Parametric Test Condition.
4. IDD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, DM, DQS, DQS , RDQS, RDQS .
6. Definitions for IDD
LOW = Vin
≤ VIL (ac) (max)
HIGH = Vin
≥ VIH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
7. The following IDD values must be derated (IDD limits increase), when TCASE
≥ 85°C IDD2P must be derated by 20 %;
IDD3P(slow) must be derated by 30 % and IDD6 must be derated by 80 %. (IDD6 will increase by this amount if TCASE < 85°C
and the 2X refresh option is still enabled)
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