參數(shù)資料
型號: W83627SF
英文描述: W83627F plus Smart Card Reader Interface. VID Control. GP I/O?
中文描述: W83627F加上智能卡閱讀器接口。 VID控制。大獎(jiǎng)賽的I / O?
文件頁數(shù): 61/147頁
文件大?。?/td> 1348K
代理商: W83627SF
W83627SF
PRELIMINARY
Publication Release Date: Nov. 2000
- 54 - Revision 0.60
4.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
1
2
3
4
5
6
7
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
0
0
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out
interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 4-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Interrupt Source
No Interrupt pending
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
RBR Data Ready
1. RBR data ready
2. FIFO interrupt active level
reached
FIFO Data Timeout
Data present in RX FIFO for 4
characters period of time since
last access of RX FIFO.
TBR Empty
TBR empty
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt
priority
Interrupt Type
Clear Interrupt
0
0
0
1
0
1
1
0
-
-
-
First
UART Receive
Status
Read USR
0
1
0
0
Second
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1
1
0
0
Second
0
0
1
0
Third
1. Write data into TBR
2. Read ISR (if priority is
third)
Read HSR
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
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