參數(shù)資料
型號: W83627SF
英文描述: W83627F plus Smart Card Reader Interface. VID Control. GP I/O?
中文描述: W83627F加上智能卡閱讀器接口。 VID控制。大獎賽的I / O?
文件頁數(shù): 104/147頁
文件大?。?/td> 1348K
代理商: W83627SF
W83627SF
PRELIMINARY
Publication Release Date: Nov. 2000
Revision 0.60
- 97 -
11.6 Smart Card Control Register (SCCR, write only at "base address + 3")
The Smart Card
Control Register controls and defines the parity bit protocol for asynchronous data
communications.
Parity Bit Enable (PBE)
Even Parity Enable (EPE)
Baud rate Divisor Latch Access Bit (BDLAB)
7
6
0
5
0
4
3
2
0
1
1
0
1
Bit 7: BDLAB. When this bit is set to a logical 1 designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation. When
this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt
Control Register can be accessed.
Bit 6 - 5: Reserved. Always 0 when read.
Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3
is programmed. When this bit is set, an even number of logic 1's are sent or checked. When the
bit is reset, an odd number of logic 1's are sent or checked.
Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT will
be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same position
as the transmitter will be detected.
Bit 2 – 0: Reserved. Bit 2 is always 0 and bit 1 – 0 are always 1 when read.
11.7 Interrupt Enable Register (IER, at "base address + 4")
This register contains global interrupt enable bit of Smart Card interface.
IRQ enable
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
Bit 7 - 4: Reserved. Always 0 when read.
Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1.
Bit 2 – 0: Reserved. Always 0 when read.
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