參數(shù)資料
型號: W83627SF
英文描述: W83627F plus Smart Card Reader Interface. VID Control. GP I/O?
中文描述: W83627F加上智能卡閱讀器接口。 VID控制。大獎賽的I / O?
文件頁數(shù): 129/147頁
文件大?。?/td> 1348K
代理商: W83627SF
W83627SF
PRELIMINARY
Publication Release Date: Nov. 2000
- 122 - Revision 0.60
CRF7 (Default 0x00)
Bit 7
: Mouse interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Mouse interrupt
= 0 Watch Dog Timer is not affected by Mouse interrupt
: Keyboard interrupt reset Enable or Disable
= 1 Watch Dog Timer is reset upon a Keyboard interrupt
= 0 Watch Dog Timer is not affected by Keyboard interrupt
: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
Bit 3 -0
: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
Bit 6
Bit 5
Bit 4
13.10 Logical Device 9 (GPIO Port 3,4 are powered by standby source VSB)
CR30 (Default 0x02)
Bit 7 - 1
: Reserved.
Bit 1
= 1 Activate GP4.
= 0 GP4 is inactive.
Bit 0
= 1 Activate GPIO3.
= 0 GPIO3 is inactive.
CR60, CR 61 (Default 0x02, 0x90 if PNPCSV = 0 during POR, default 0x00 otherwise)
These two registers select the GP3, GP4 port base address [0x100:0xFFF] on 2 byte boundary. GP3
is accessible through "base address" and GP4 is accessible through "base address" +1.
CRF0 (GP30-GP35 I/O selection register. Default 0xFF Bit 7 - 6: Reserved)
When set to a '1', respective GPIO port is programmed as an input port.
When set to a '0', respective GPIO port is programmed as an output port.
CRF1 (GP30-GP35 data register. Default 0x00 Bit 7 - 6: Reserved)
If a port is programmed to be an output port, then its respective bit can be read/written.
If a port is programmed to be an input port, then its respective bit can only be read.
CRF2 (GP30-GP35 inversion register. Default 0x00 Bit 7 - 6: Reserved)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
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