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參數(shù)資料
| 型號： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
C
O
MMA
N
D
R
E
AD
NOP
NOP
NOP
C
L =
2
.
5
D
ON'T
CAR
E
T
RA
N
S
ITIONING
DA
T
A
DQ
DQS
T
0
T
1
T
2
T
2
n
T
3
T
3
n
C
O
MMA
N
D
R
E
AD
NOP
NOP
NOP
C
L =
2
DQ
DQS
C
LK
C
LK
T
0
T
1
T
2
T
2
n
T
3
T
3
n
B
urst Length = 4 in the cases shown
S
hown with nominal t
AC
and nominal t
DSDQ
DA
T
A
C
LK
C
LK
FIGURE 4 – CAS LATENCY
FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
DLL
Enable
Disable
DLL
DS
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Extended Mode
Address Bus
Operating Mode
A
10
A
11
11
01
BA
0
BA
1
E0
0
1
Drive Strength
Normal
Reduced
E1
0
1
Operating Mode
Reserved
Reserved
E1, E0
Valid
-
E12
0
-
E10
0
-
E9
0
-
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
A
12
E11
0
-
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
E2
0
-
in conjunction with a spe cif c READ or WRITE command.
A precharge of the bank/row that is ad dressed with the
READ or WRITE com mand is au o mat cal y performed
upon com ple ion of the READ or WRITE burst. AUTO
PRECHARGE is non per sis ent in that it is either en abled
or dis abled for each in di vid u al READ or WRITE command.
The device sup ports concurrent auto precharge if the
com mand to the oth er bank does not in er upt the data
transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was is sued at the earliest possible
time, without violating t
RAS
(MIN).The user must not is sue
an oth er com mand to the same bank until the precharge
time (t
RP
) is com plet ed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
AUTO REFRESH
AUTO REFRESH is used during normal op er a ion of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) RE FRESH in con ven ion al DRAMs. This com mand
is non per sis ent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
con rol er. This makes the address bits “Don’t Care” during
an AUTO RE FRESH command. Each DDR SDRAM
requires AUTO RE FRESH cycles at an average interval
of 7.8125μs (maximum).
To allow for improved efficiency in scheduling and
switch ng between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, mean ng that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
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相關代理商/技術參數(shù) |
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| W3E32M64S-266BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-266BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-266SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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