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參數(shù)資料
| 型號： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
13
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
NOTES:
1.
2.
All voltages referenced to V
SS
.
Tests for AC timing, I
CC
, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related speci
fi
cations
and device operation are guaranteed for the full voltage range speci
fi
ed.
Outputs measured with equivalent load:
3.
4.
AC timing and I
CC
tests may use a V
IL
-to-V
IH
swing of up to 1.5V in the test
environment, but input timing is still referenced to V
REF
(or to the crossing point for
CK/CK#), and parameter speci
fi
cations are guaranteed for the speci
fi
ed AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between V
IL
(AC) and V
IH
(AC).
The AC and DC input level speci
fi
cations are as de
fi
ned in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
V
REF
is expected to equal V
CCQ/2
of the transmitting device and to track variations in
the DC level of the same. Peak-to-peak noise (noncommon mode) on V
REF
may not
exceed ±2 percent of the DC value. Thus, from V
CCQ/2
, V
REF
is allowed ±25mV for
DC error and an additional ±25mV for AC noise. This measurement is to be taken
at the nearest V
REF
by-pass capacitor.
V
TT
is not applied directly to the device. V
TT
is a system supply for signal
termination resistors, is expected to be set equal to V
REF
and must track variations
in the DC level of V
REF
.
V
ID
is the magnitude of the difference between the input level on CK and the input
level on CK#.
The value of V
IX
and V
MP
are expected to equal V
CCQ/2
of the transmitting device
and must track variations in the DC level of the same.
10. I
CC
is dependent on output loading and cycle rates. Speci
fi
ed values are obtained
with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. I
CC
speci
fi
cations are tested after the device is properly initialized, and is averaged
at the de
fi
ned cycle rate.
13. This parameter is not tested but guaranteed by design. t
A
= 25°C, f = 1 MHz
14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew rate
is less than 0.5V/ns, timing must be derated: t
IS
has an additional 50 ps per each
100mV/ns reduction in slew rate from the 500mV/ns. t
IH
has 0ps added, that is, it
remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
V
REF
.
5.
6.
7.
8.
9.
16. Inputs are not recognized as valid until V
REF
stabilizes once initialized, including
SELF REFRESH mode, V
REF
must be powered within speci
fi
ed range. Exception:
during the period before V
REF
stabilizes, CKE
≤
0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is V
TT
.
18. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a speci
fi
c voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The intent of the Don't Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above V
IH
DC (MIN) then it must not transition low (below
V
IH
DC) prior to t
DQSH
(MIN).
20. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on t
DQSS
.
22. MIN (t
RC
or t
RFC
) for I
CC
measurements is the smallest multiple of t
CK
that meets
the minimum absolute value for the respective parameter. t
RAS
(MAX) for I
CC
measurements is the largest multiple of t
CK
that meets the maximum absolute value
for t
RAS
.
23. The refresh period 64ms. This equates to an average refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be asserted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
25. The valid data window is derived by achieving other speci
fi
cations - t
HP
(t
CK/2
),
t
DQSQ
, and t
QH
(t
QH
= t
HP
- t
QHS
). The data valid window derates directly porportional
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with DQ8-
DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (t
RFC
[MIN]) else CKE is LOW (i.e., during
standby).
160
140
120
100
80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
I
O
Maximum
Nominal high
Nominal low
Minimum
50
Output
(V
)
V
TT
FIGURE A – PULL-DOWN CHARACTERISTICS
FIGURE B – PULL-UP CHARACTERISTICS
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
V
CCQ -
V
OUT
(V)
I
O
Maximum
Nominal high
Nominal low
Minimum
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| W3E32M64S-266BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
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| W3E32M64S-266SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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