參數(shù)資料
型號: W3E32M64S-250SBM
英文描述: 32Mx64 DDR SDRAM
中文描述: 32Mx64 DDR內(nèi)存
文件頁數(shù): 12/17頁
文件大?。?/td> 735K
代理商: W3E32M64S-250SBM
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1-5, 14-17, 33)
Parameter
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
Symbol
t
AC
t
CH
t
CL
t
CK (3)
t
CK (2.5)
t
CK (2)
t
DH
t
DS
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
t
DQSQ
t
DQSS
t
DSS
t
DSH
t
HP
t
HZ
t
LZ
t
IHF
t
ISF
t
IHS
t
ISS
t
MRD
t
QH
t
QHS
t
RAS
t
RAP
t
RC
t
RFC
t
RCD
t
RP
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
NA
t
REFC
333 Mbs CL 3 (53)
266 Mbs CL2.5
Mn
-0.70
0.45
0.45
6
7.5
10
0.45
0.45
1.75
-0.6
0.35
0.35
266 Mbs CL 2.5
200 Mbs CL2
Mn
-0.75
0.45
0.45
250 Mbs CL2.5
200 Mbs CL2
Mn
-0.8
0.45
0.45
200 Mbs CL2.5
150 Mbs CL2
Mn
-0.8
0.45
0.45
Max
+0.70
0.55
0.55
13
13
13
Max
+0.75
0.55
0.55
Max
+0.8
0.55
0.55
Max
+0.8
0.55
0.55
Units
ns
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
ns
μs
Clock cycle time
CL = 3 (45, 51, 53)
CL = 2.5 (45, 51)
CL = 2 (45, 51)
7.5
10
0.5
0.5
1.75
-0.75
0.35
0.35
13
13
8
10
0.6
0.6
2
-0.8
0.35
0.35
13
13
10
13
0.6
0.6
2
-0.8
0.35
0.35
13
15
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to
fi
rst DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 42)
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to
fi
rst DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (49)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (43)
DQS read postamble (43)
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
REFRESH to REFRESH command interval (23) (commercial and
Industrial)
REFRESH to REFRESH command interval (Military temperature)
Average periodic refresh interval (23) (commercial and Industrial)
Average periodic refresh interval (Military temperature)
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
+0.6
+0.75
+0.8
+0.8
0.45
1.25
0.5
1.25
0.6
1.25
0.6
1.25
0.75
0.2
0.2
t
CH
,t
CL
0.75
0.2
0.2
t
CH
,t
CL
0.75
0.2
0.2
t
CH
,t
CL
0.75
0.2
0.2
t
CH
,t
CL
+0.70
+0.75
+0.8
+0.8
-0.70
0.75
0.75
0.8
0.8
12
t
HP
-t
QHS
0.55
42
15
60
72
15
15
0.9
0.4
12
0.25
0
0.4
15
1
-0.75
0.90
0.90
1
1
15
t
HP
-t
QHS
-0.8
1.1
1.1
1.1
1.1
16
t
HP
-t
QHS
-0.8
1.1
1.1
1.1
1.1
16
t
HP
-t
QHS
0.75
120,000
1
1
70,000
40
20
65
75
20
20
0.9
0.4
15
0.25
0
0.4
15
1
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
1
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
0.4
15
1
120,000
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
0.6
0.6
0.6
0.6
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
t
QH -
t
DQSQ
70.3
70.3
70.3
70.3
t
REFC
t
REFI
t
REFI
t
VTD
t
XSNR
t
XSRD
35
7.8
3.9
35
7.8
3.9
35
7.8
3.9
35
7.8
3.9
μs
μs
μs
ns
ns
t
CK
0
75
200
0
75
200
0
80
200
0
80
200
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