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參數(shù)資料
| 型號： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
A
0-12
A
0-12
BA
0-1
BA
0-1
CLK
CLK
0
CLK
CAS
DQ
0
DQ
15
CKE
0
CKE
CS
0
CS
DQML
0
DQML
DQMH
0
DQMH
RAS
1
CAS
1
WE
1
DQ
0
Y
=
Y
=
DQ
15
WE
U1
RAS
A
0-12
BA
0-1
CLK
CLK
1
CLK
CAS
DQ
16
Y
=
Y
=
DQ
31
RAS
0
CAS
0
WE
0
DQ
0
Y
=
Y
=
DQ
15
WE
U0
RAS
CKE
1
CKE
CS
1
CS
DQML
1
DQML
DQMH
1
DQMH
RAS
2
CAS
2
WE
2
DQ
0
Y
=
Y
=
DQ
15
WE
U2
RAS
A
0-12
BA
0-1
CLK
CLK
2
CLK
CAS
DQ
32
Y
=
Y
=
DQ
47
CKE
2
CKE
CS
2
CS
DQML
2
DQML
DQMH
2
DQMH
RAS
3
CAS
3
WE
3
DQ
0
Y
=
Y
=
DQ
15
WE
U3
RAS
A
0-12
BA
0-1
CLK
CLK
3
CKE
3
CLK
CKE
CAS
DQ
48
Y
=
Y
=
DQ
63
CS
3
CS
DQML
DQMH
DQSL
3
DQSH
3
DQSL
DQSH
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
Y
=
CLK
3
V
REF
DQSL
2
DQSL
DQSH
2
DQSH
V
REF
DQSL
1
DQSL
DQSH
1
DQSH
V
REF
DQSL
0
DQSL
DQSH
0
DQSH
V
REF
CLK
2
CLK
1
CLK
0
V
REF
DQML
3
DQMH
3
FIGURE 2 FUNCTIONAL BLOCK DIAGRAM
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
pre defined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to V
CC
and V
CCQ
simultaneously, and
then to V
REF
(and to the system V
TT
). V
TT
must be applied
after V
CCQ
to avoid device latch-up, which may cause
per ma nent dam age to the device. V
REF
can be applied any
time after V
CCQ
but is expected to be nominally coincident
with V
TT
. Except for CKE, inputs are not recognized as
valid until after V
REF
is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
CC
is applied.
After CKE passes through V
IH
, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during power-
up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read ac cess). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200μs delay prior
to applying an executable com mand.
Once the 200μs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REG S TER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, fol owed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (t
RFC
must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa am e ers without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal op er a ion.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E32M64S-266BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-266BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-266SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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