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參數(shù)資料
| 型號(hào)： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
TABLE 1 – BURST DEFINITION
NOTES:
1.
For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
2.
3.
4.
FIGURE 3 MODE REGISTER DEFINITION
M3 = 0
2
4
8
R
eserved
R
eserved
R
eserved
M3 = 1
2
4
R
eserved
R
eserved
R
eserved
R
eserved
Operating Mode
Normal Operation
Normal Operation/
R
eset
D
LL
A
ll other states reserved
0
0
V
alid
V
alid
0
1
Burst Type
S
equential
Interleaved
CAS Latency
R
eserved
R
eserved
2
R
eserved
R
eserved
2
.
5
R
eserved
Burst Length
M0
0
1
0
1
0
1
0
1
B
urst Length
CAS
Latency
B
T
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
M
ode
R
egister (
M
x)
A
ddress
B
us
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Operating
M
ode
A
10
A
11
*
M1
4 and
M13
(
BA0
and
BA1
must be
"
0
,
0
" to select
the base mode register
(vs. the extended
mode register).
0
*
0
*
BA
0
BA
1
R
eserved
R
eserved
R
eserved
R
eserved
M9
M10
M11
0
0
0
1
0
0
0
0
-
-
-
-
-
-
A
12
M12
0
0
-
HIGH, the cor e spond ng data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (t
RP
) after the PRECHARGE command is
is sued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
pa am e ers. Input A10 de er mines wheth er one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, in puts BA0, BA1 select the
bank. Oth er wise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be ac i vat ed pri or to any READ or WRITE commands
being is sued to that bank. A PRECHARGE com mand will
be treat ed as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
pro cess of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same in di vid u al-bank PRECHARGE function de scribed
above, but with out re quir ng an explicit command. This is
ac com plished by using A10 to enable AUTO PRECHARGE
Burst
Length
Starting Column
Address
Order of Accesses With n a Burst
Type = Sequential
Type = In er eaved
2
A0
0
1
0-1
1-0
0-1
1-0
4
A1
0
0
1
1
A0
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
8
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
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| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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