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| 型號： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
14
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC
level, V
IL
(AC) or V
IH
(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
level, V
IL
(DC) or V
IH
(DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK input slew rate must be
≥
1V/ns (
≥
2V/ns differentially).
31. DQ and DM# input slew rates must not deviate from DQS by more than 10%. If the
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to t
DS
and t
DH
for each 100mV/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
32. V
CC
must not vary more than 4% if CKE is not active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
34. t
HP
min is the lesser of t
CL
minimum and t
CH
minimum actually applied to the device
CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
t
RAS
(MIN) can be satis
fi
ed prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive. The average cannot be below the 2.5V minimum.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure D.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 V, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from a minimum V
CC
level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide signi
fi
cantly different voltage values.
40. V
IH
overshoot: V
IH
(MAX) = V
CCQ+1.5V
for a pulse width
≤
3ns and the pulse width
can not be greater than 1/3 of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -1.5V for a
pulse width
≤
3ns and the pulse width cannot be greater than 1/3 of the cycle rate.
41. V
CC
and V
CCQ
must track each other.
42. t
HZ
(MAX) will prevail over t
DQSCK
(MAX) + t
RPST
(MAX) condition. t
LZ
(MIN) will
prevail over t
DQSCK
(MIN) + t
RPRE
(MAX) condition.
43. t
RPST
end point and t
RPRE
bigin point are not referenced to a speci
fi
c voltage level
but specify when the device output is no longer driving (t
RPST
), or begins driving
(t
RPRE
).
44. During initialization, V
CCQ
, V
TT
, and V
REF
must be equal to or less than V
CC
+ 0.3V.
Alternatively, V
TT
may be 1.35V maximum during power up, even if V
CC
/V
CCQ
are 0
volts, provided a minimum of 42 ohms of series resistance is used between the V
TT
supply and the input pin.
45. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not re
fl
ect this option.
46. When an input signal is HIGH or LOW, it is de
fi
ned as a steady state logic HIGH or
LOW.
47. Random addressing changing 50% of data changing at every transfer.
48. Random addressing changing 100% of data changing at every transfer.
49. CKE must be active (high) during the entire time a refresh command is executed.
FIGURE C – PULL-DOWN CHARACTERISTICS
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
I
O
Maximum
Nominal high
Nominal low
Minimum
FIGURE D – PULL-UP CHARACTERISTICS
0.0
0.5
1.0
1.5
2.0
2.5
V
CCQ -
V
OUT
(V)
I
O
Maximum
Nominal high
Nominal low
Minimum
0
-10
-20
-30
-40
-50
-60
-70
-80
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| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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