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參數(shù)資料
| 型號(hào)： | W3E32M64S-250SBM |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大?。?/td> | 735K |
| 代理商： | W3E32M64S-250SBM |
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White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3E32M64S -X S BX
July 2006
Rev. 5
I/O
Count
I/O
Count
Area
4 x 265mm
2
= 1060mm
2
4 x 66 pins = 264 pins
286mm
2
208 Balls
73%
21%
Area
4 x 125mm
2
= 500mm
2
4 x 60 balls = 240 balls
286mm
2
208 Balls
43%
13%
S
A
V
I
N
G
S
Actual Size
W3E32M64S-XSBX
13
22
TSOP Approach (mm)
11.9
22.3
11.9
66
TSOP
66
TSOP
66
TSOP
66
TSOP
11.9
11.9
S
A
V
I
N
G
S
CSP Approach (mm)
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
60
FBGA
10.0
12.5
Actual Size
W3E32M64S-XSBX
DENSITY COMPARISONS
Read and write accesses to the DDR SDRAM are burst
ori ent ed; accesses start at a selected location and continue
for a pro grammed number of locations in a programmed
sequence. Accesses begin with the registration of an
AC TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The ad dress bits registered
coincident with the READ or WRITE com mand are used
to select the bank and the starting column location for the
burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge func ion may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
The pipelined, multibank architecture of DDR SDRAMs
al ows for concurrent operation, thereby providing high
ef ec ive band width by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DE SCRIP TION
Read and write accesses to the DDR SDRAM are burst
ori ent ed; accesses start at a selected location and continue
for a pro grammed number of locations in a pro grammed
se quence. Ac cess es begin with the registration of an
AC TIVE com mand which is then followed by a READ or
WRITE com mand. The address bits registered coincident
with the AC TIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE com mand are used to select the
start ng column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initial-
ized. The following sections provide detailed information
cov er ng device initialization, register de
fi
nition, command
de scrip ions and de vice operation.
13
22
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3E32M64S-266SBC | 32Mx64 DDR SDRAM |
| W3E32M64S-XSBX | DDR SDRAM STACKED MCP |
| W3E64M72S-266ESI | 64Mx72 DDR SDRAM |
| W3E64M72S-266ESM | 64Mx72 DDR SDRAM |
| W3E64M72S-333BC | 64Mx72 DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E32M64S-266BC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-266BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-266SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-266SBI | 制造商:White Electronic Designs 功能描述:32M X 64 DDR, 2.5V, 266 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
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