參數(shù)資料
型號： W25Q80BWZPIP
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 8M X 1 SPI BUS SERIAL EEPROM, PDSO8
封裝： 6 X 5 MM, GREEN , PLASTIC, WSON-8
文件頁數(shù)： 5/71頁
文件大?。?/td> 0K
代理商： W25Q80BWZPIP
W25Q80BW
Publication Release Date: January 26, 2011
- 13 -
Preliminary - Revision A
8.1.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled.
When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are
disabled.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
S7
S6
S5
S4
S3
S2
S1
S0
SRP0 SEC
TB
BP2
BP1
BP0
WEL BUSY
STATUS REGISTER PROTECT 0
(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
S7
S6
S5
S4
S3
S2
S1
S0
SRP0 SEC
TB
BP2
BP1
BP0
WEL BUSY
STATUS REGISTER PROTECT 0
(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
Figure 3a. Status Register-1
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
LB0
QE
SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(non-volatile)
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
LB0
QE
SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(non-volatile)
Figure 3b. Status Register-2
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