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參數(shù)資料
| 型號： | W25Q80BWZPIP |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 1 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 6 X 5 MM, GREEN , PLASTIC, WSON-8 |
| 文件頁數(shù)： | 16/71頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W25Q80BWZPIP |
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W25Q80BW
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and
SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Please refer to 8.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits
are 0.
15 14 13 12 11 10
9
8
Status Register 1
Status Register 2
15 14 13 12 11 10
9
8
Status Register 1
Status Register 2
Figure 8. Write Status Register Instruction Sequence Diagram
Publication Release Date: January 26, 2011
- 23 -
Preliminary - Revision A
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| W25S243AF-12 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
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